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      1 ; RUN: llc < %s -march=x86 -mattr=+sse2,+ssse3 | FileCheck %s
      2 ; There are no MMX operations in @t1
      3 
      4 define void  @t1(i32 %a, x86_mmx* %P) nounwind {
      5 ; CHECK-LABEL: t1:
      6 ; CHECK:       # BB#0:
      7 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
      8 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
      9 ; CHECK-NEXT:    shll $12, %ecx
     10 ; CHECK-NEXT:    movd %ecx, %xmm0
     11 ; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
     12 ; CHECK-NEXT:    movq %xmm0, (%eax)
     13 ; CHECK-NEXT:    retl
     14  %tmp12 = shl i32 %a, 12
     15  %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
     16  %tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0
     17  %tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx
     18  store x86_mmx %tmp23, x86_mmx* %P
     19  ret void
     20 }
     21 
     22 define <4 x float> @t2(<4 x float>* %P) nounwind {
     23 ; CHECK-LABEL: t2:
     24 ; CHECK:       # BB#0:
     25 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
     26 ; CHECK-NEXT:    movaps (%eax), %xmm1
     27 ; CHECK-NEXT:    xorps %xmm0, %xmm0
     28 ; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
     29 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
     30 ; CHECK-NEXT:    retl
     31   %tmp1 = load <4 x float>, <4 x float>* %P
     32   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
     33   ret <4 x float> %tmp2
     34 }
     35 
     36 define <4 x float> @t3(<4 x float>* %P) nounwind {
     37 ; CHECK-LABEL: t3:
     38 ; CHECK:       # BB#0:
     39 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
     40 ; CHECK-NEXT:    movapd (%eax), %xmm0
     41 ; CHECK-NEXT:    xorpd %xmm1, %xmm1
     42 ; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
     43 ; CHECK-NEXT:    retl
     44   %tmp1 = load <4 x float>, <4 x float>* %P
     45   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
     46   ret <4 x float> %tmp2
     47 }
     48 
     49 define <4 x float> @t4(<4 x float>* %P) nounwind {
     50 ; CHECK-LABEL: t4:
     51 ; CHECK:       # BB#0:
     52 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
     53 ; CHECK-NEXT:    movaps (%eax), %xmm0
     54 ; CHECK-NEXT:    xorps %xmm1, %xmm1
     55 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[1,0]
     56 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
     57 ; CHECK-NEXT:    retl
     58   %tmp1 = load <4 x float>, <4 x float>* %P
     59   %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
     60   ret <4 x float> %tmp2
     61 }
     62 
     63 define <16 x i8> @t5(<16 x i8> %x) nounwind {
     64 ; CHECK-LABEL: t5:
     65 ; CHECK:       # BB#0:
     66 ; CHECK-NEXT:    psrlw $8, %xmm0
     67 ; CHECK-NEXT:    retl
     68   %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
     69   ret <16 x i8> %s
     70 }
     71 
     72 define <16 x i8> @t6(<16 x i8> %x) nounwind {
     73 ; CHECK-LABEL: t6:
     74 ; CHECK:       # BB#0:
     75 ; CHECK-NEXT:    psrlw $8, %xmm0
     76 ; CHECK-NEXT:    retl
     77   %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
     78   ret <16 x i8> %s
     79 }
     80 
     81 define <16 x i8> @t7(<16 x i8> %x) nounwind {
     82 ; CHECK-LABEL: t7:
     83 ; CHECK:       # BB#0:
     84 ; CHECK-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2]
     85 ; CHECK-NEXT:    retl
     86   %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
     87   ret <16 x i8> %s
     88 }
     89 
     90 define <16 x i8> @t8(<16 x i8> %x) nounwind {
     91 ; CHECK-LABEL: t8:
     92 ; CHECK:       # BB#0:
     93 ; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
     94 ; CHECK-NEXT:    retl
     95   %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
     96   ret <16 x i8> %s
     97 }
     98 
     99 define <16 x i8> @t9(<16 x i8> %x) nounwind {
    100 ; CHECK-LABEL: t9:
    101 ; CHECK:       # BB#0:
    102 ; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
    103 ; CHECK-NEXT:    retl
    104   %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 undef, i32 undef>
    105   ret <16 x i8> %s
    106 }
    107