1 /************************************************************************** 2 3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6 All Rights Reserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining 9 a copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sublicense, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice (including the 17 next paragraph) shall be included in all copies or substantial 18 portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28 **************************************************************************/ 29 30 /* 31 * Authors: 32 * Keith Whitwell <keith (at) tungstengraphics.com> 33 */ 34 35 #include "main/glheader.h" 36 #include "main/mtypes.h" 37 #include "main/colormac.h" 38 #include "main/enums.h" 39 #include "main/imports.h" 40 #include "main/macros.h" 41 #include "main/simple_list.h" 42 43 #include "math/m_xform.h" 44 45 #include "swrast_setup/swrast_setup.h" 46 47 #include "tnl/tnl.h" 48 #include "tnl/t_context.h" 49 #include "tnl/t_pipeline.h" 50 51 #include "radeon_context.h" 52 #include "radeon_ioctl.h" 53 #include "radeon_state.h" 54 #include "radeon_swtcl.h" 55 #include "radeon_tcl.h" 56 #include "radeon_debug.h" 57 58 59 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */ 60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */ 61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */ 62 63 /*********************************************************************** 64 * Initialization 65 ***********************************************************************/ 66 67 #define EMIT_ATTR( ATTR, STYLE, F0 ) \ 68 do { \ 69 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ 70 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ 71 rmesa->radeon.swtcl.vertex_attr_count++; \ 72 fmt_0 |= F0; \ 73 } while (0) 74 75 #define EMIT_PAD( N ) \ 76 do { \ 77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ 78 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ 79 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ 80 rmesa->radeon.swtcl.vertex_attr_count++; \ 81 } while (0) 82 83 static GLuint radeon_cp_vc_frmts[3][2] = 84 { 85 { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 }, 86 { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 }, 87 { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 }, 88 }; 89 90 static void radeonSetVertexFormat( struct gl_context *ctx ) 91 { 92 r100ContextPtr rmesa = R100_CONTEXT( ctx ); 93 TNLcontext *tnl = TNL_CONTEXT(ctx); 94 struct vertex_buffer *VB = &tnl->vb; 95 GLbitfield64 index_bitset = tnl->render_inputs_bitset; 96 int fmt_0 = 0; 97 int offset = 0; 98 99 /* Important: 100 */ 101 if ( VB->NdcPtr != NULL ) { 102 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; 103 } 104 else { 105 VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; 106 } 107 108 assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); 109 rmesa->radeon.swtcl.vertex_attr_count = 0; 110 111 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to 112 * build up a hardware vertex. 113 */ 114 if ( !rmesa->swtcl.needproj || 115 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) { 116 /* for projtex */ 117 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, 118 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 ); 119 offset = 4; 120 } 121 else { 122 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F, 123 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z ); 124 offset = 3; 125 } 126 127 rmesa->swtcl.coloroffset = offset; 128 #if MESA_LITTLE_ENDIAN 129 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, 130 RADEON_CP_VC_FRMT_PKCOLOR ); 131 #else 132 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, 133 RADEON_CP_VC_FRMT_PKCOLOR ); 134 #endif 135 offset += 1; 136 137 rmesa->swtcl.specoffset = 0; 138 if (index_bitset & 139 (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) { 140 141 #if MESA_LITTLE_ENDIAN 142 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { 143 rmesa->swtcl.specoffset = offset; 144 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, 145 RADEON_CP_VC_FRMT_PKSPEC ); 146 } 147 else { 148 EMIT_PAD( 3 ); 149 } 150 151 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) { 152 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, 153 RADEON_CP_VC_FRMT_PKSPEC ); 154 } 155 else { 156 EMIT_PAD( 1 ); 157 } 158 #else 159 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) { 160 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, 161 RADEON_CP_VC_FRMT_PKSPEC ); 162 } 163 else { 164 EMIT_PAD( 1 ); 165 } 166 167 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { 168 rmesa->swtcl.specoffset = offset; 169 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, 170 RADEON_CP_VC_FRMT_PKSPEC ); 171 } 172 else { 173 EMIT_PAD( 3 ); 174 } 175 #endif 176 } 177 178 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { 179 int i; 180 181 for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { 182 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) { 183 GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size; 184 185 switch (sz) { 186 case 1: 187 case 2: 188 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F, 189 radeon_cp_vc_frmts[i][0] ); 190 break; 191 case 3: 192 if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) { 193 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F, 194 radeon_cp_vc_frmts[i][1] ); 195 } else { 196 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F, 197 radeon_cp_vc_frmts[i][0] ); 198 } 199 break; 200 case 4: 201 if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) { 202 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F, 203 radeon_cp_vc_frmts[i][1] ); 204 } else { 205 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW, 206 radeon_cp_vc_frmts[i][1] ); 207 } 208 break; 209 default: 210 continue; 211 }; 212 } 213 } 214 } 215 216 if (rmesa->radeon.tnl_index_bitset != index_bitset || 217 fmt_0 != rmesa->swtcl.vertex_format) { 218 RADEON_NEWPRIM(rmesa); 219 rmesa->swtcl.vertex_format = fmt_0; 220 rmesa->radeon.swtcl.vertex_size = 221 _tnl_install_attrs( ctx, 222 rmesa->radeon.swtcl.vertex_attrs, 223 rmesa->radeon.swtcl.vertex_attr_count, 224 NULL, 0 ); 225 rmesa->radeon.swtcl.vertex_size /= 4; 226 rmesa->radeon.tnl_index_bitset = index_bitset; 227 radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, 228 "%s: vertex_size= %d floats\n", __FUNCTION__, rmesa->radeon.swtcl.vertex_size); 229 } 230 } 231 232 static void radeon_predict_emit_size( r100ContextPtr rmesa ) 233 { 234 235 if (!rmesa->radeon.swtcl.emit_prediction) { 236 const int state_size = radeonCountStateEmitSize( &rmesa->radeon ); 237 const int scissor_size = 8; 238 const int prims_size = 8; 239 const int vertex_size = 7; 240 241 if (rcommonEnsureCmdBufSpace(&rmesa->radeon, 242 state_size + 243 (scissor_size + prims_size + vertex_size), 244 __FUNCTION__)) 245 rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon ); 246 else 247 rmesa->radeon.swtcl.emit_prediction = state_size; 248 rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size 249 + rmesa->radeon.cmdbuf.cs->cdw; 250 } 251 } 252 253 static void radeonRenderStart( struct gl_context *ctx ) 254 { 255 r100ContextPtr rmesa = R100_CONTEXT( ctx ); 256 257 radeonSetVertexFormat( ctx ); 258 259 if (rmesa->radeon.dma.flush != 0 && 260 rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim) 261 rmesa->radeon.dma.flush( ctx ); 262 } 263 264 265 /** 266 * Set vertex state for SW TCL. The primary purpose of this function is to 267 * determine in advance whether or not the hardware can / should do the 268 * projection divide or Mesa should do it. 269 */ 270 void radeonChooseVertexState( struct gl_context *ctx ) 271 { 272 r100ContextPtr rmesa = R100_CONTEXT( ctx ); 273 TNLcontext *tnl = TNL_CONTEXT(ctx); 274 275 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT]; 276 277 se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 278 RADEON_VTX_Z_PRE_MULT_1_OVER_W0 | 279 RADEON_VTX_W0_IS_NOT_1_OVER_W0); 280 281 /* We must ensure that we don't do _tnl_need_projected_coords while in a 282 * rasterization fallback. As this function will be called again when we 283 * leave a rasterization fallback, we can just skip it for now. 284 */ 285 if (rmesa->radeon.Fallback != 0) 286 return; 287 288 /* HW perspective divide is a win, but tiny vertex formats are a 289 * bigger one. 290 */ 291 292 if ((0 == (tnl->render_inputs_bitset & 293 (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX) 294 | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)))) 295 || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) { 296 rmesa->swtcl.needproj = GL_TRUE; 297 se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 298 RADEON_VTX_Z_PRE_MULT_1_OVER_W0); 299 } 300 else { 301 rmesa->swtcl.needproj = GL_FALSE; 302 se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0); 303 } 304 305 _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj ); 306 307 if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) { 308 RADEON_STATECHANGE( rmesa, set ); 309 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt; 310 } 311 } 312 313 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset) 314 { 315 r100ContextPtr rmesa = R100_CONTEXT(ctx); 316 317 318 319 radeonEmitState(&rmesa->radeon); 320 radeonEmitVertexAOS( rmesa, 321 rmesa->radeon.swtcl.vertex_size, 322 rmesa->radeon.swtcl.bo, 323 current_offset); 324 325 326 radeonEmitVbufPrim( rmesa, 327 rmesa->swtcl.vertex_format, 328 rmesa->radeon.swtcl.hw_primitive, 329 rmesa->radeon.swtcl.numverts); 330 if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw ) 331 WARN_ONCE("Rendering was %d commands larger than predicted size." 332 " We might overflow command buffer.\n", 333 rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction ); 334 335 336 rmesa->radeon.swtcl.emit_prediction = 0; 337 338 } 339 340 /* 341 * Render unclipped vertex buffers by emitting vertices directly to 342 * dma buffers. Use strip/fan hardware primitives where possible. 343 * Try to simulate missing primitives with indexed vertices. 344 */ 345 #define HAVE_POINTS 1 346 #define HAVE_LINES 1 347 #define HAVE_LINE_STRIPS 1 348 #define HAVE_TRIANGLES 1 349 #define HAVE_TRI_STRIPS 1 350 #define HAVE_TRI_STRIP_1 0 351 #define HAVE_TRI_FANS 1 352 #define HAVE_QUADS 0 353 #define HAVE_QUAD_STRIPS 0 354 #define HAVE_POLYGONS 0 355 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */ 356 #define HAVE_ELTS 0 357 358 static const GLuint hw_prim[GL_POLYGON+1] = { 359 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT, 360 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 361 0, 362 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP, 363 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 364 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP, 365 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN, 366 0, 367 0, 368 0 369 }; 370 371 static INLINE void 372 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim ) 373 { 374 RADEON_NEWPRIM( rmesa ); 375 rmesa->radeon.swtcl.hw_primitive = hw_prim[prim]; 376 // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start); 377 } 378 379 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size ) 380 { 381 void *rv; 382 do { 383 radeon_predict_emit_size( rmesa ); 384 rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size ); 385 } while (!rv); 386 return rv; 387 } 388 389 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx) 390 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim ) 391 #define FLUSH() RADEON_NEWPRIM( rmesa ) 392 #define GET_CURRENT_VB_MAX_VERTS() 10\ 393 // (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4)) 394 #define GET_SUBSEQUENT_VB_MAX_VERTS() \ 395 ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4)) 396 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 ) 397 #define EMIT_VERTS( ctx, j, nr, buf ) \ 398 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf) 399 400 #define TAG(x) radeon_dma_##x 401 #include "tnl_dd/t_dd_dmatmp.h" 402 403 404 /**********************************************************************/ 405 /* Render pipeline stage */ 406 /**********************************************************************/ 407 408 409 static GLboolean radeon_run_render( struct gl_context *ctx, 410 struct tnl_pipeline_stage *stage ) 411 { 412 r100ContextPtr rmesa = R100_CONTEXT(ctx); 413 TNLcontext *tnl = TNL_CONTEXT(ctx); 414 struct vertex_buffer *VB = &tnl->vb; 415 tnl_render_func *tab = TAG(render_tab_verts); 416 GLuint i; 417 418 if (rmesa->radeon.swtcl.RenderIndex != 0 || 419 !radeon_dma_validate_render( ctx, VB )) 420 return GL_TRUE; 421 422 radeon_prepare_render(&rmesa->radeon); 423 if (rmesa->radeon.NewGLState) 424 radeonValidateState( ctx ); 425 426 tnl->Driver.Render.Start( ctx ); 427 428 for (i = 0 ; i < VB->PrimitiveCount ; i++) 429 { 430 GLuint prim = VB->Primitive[i].mode; 431 GLuint start = VB->Primitive[i].start; 432 GLuint length = VB->Primitive[i].count; 433 434 if (!length) 435 continue; 436 437 radeon_print(RADEON_SWRENDER, RADEON_NORMAL, 438 "radeon_render.c: prim %s %d..%d\n", 439 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK), 440 start, start+length); 441 442 if (length) 443 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim ); 444 } 445 446 tnl->Driver.Render.Finish( ctx ); 447 448 return GL_FALSE; /* finished the pipe */ 449 } 450 451 452 453 const struct tnl_pipeline_stage _radeon_render_stage = 454 { 455 "radeon render", 456 NULL, 457 NULL, 458 NULL, 459 NULL, 460 radeon_run_render /* run */ 461 }; 462 463 464 /**************************************************************************/ 465 466 467 static const GLuint reduced_hw_prim[GL_POLYGON+1] = { 468 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT, 469 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 470 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 471 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE, 472 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 473 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 474 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 475 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 476 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST, 477 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 478 }; 479 480 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim ); 481 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim ); 482 static void radeonResetLineStipple( struct gl_context *ctx ); 483 484 485 /*********************************************************************** 486 * Emit primitives as inline vertices * 487 ***********************************************************************/ 488 489 #undef LOCAL_VARS 490 #undef ALLOC_VERTS 491 #define CTX_ARG r100ContextPtr rmesa 492 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size 493 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 ) 494 #undef LOCAL_VARS 495 #define LOCAL_VARS \ 496 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 497 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; 498 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int))) 499 #define VERTEX radeonVertex 500 #undef TAG 501 #define TAG(x) radeon_##x 502 #include "tnl_dd/t_dd_triemit.h" 503 504 505 /*********************************************************************** 506 * Macros for t_dd_tritmp.h to draw basic primitives * 507 ***********************************************************************/ 508 509 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d ) 510 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c ) 511 #define LINE( a, b ) radeon_line( rmesa, a, b ) 512 #define POINT( a ) radeon_point( rmesa, a ) 513 514 /*********************************************************************** 515 * Build render functions from dd templates * 516 ***********************************************************************/ 517 518 #define RADEON_TWOSIDE_BIT 0x01 519 #define RADEON_UNFILLED_BIT 0x02 520 #define RADEON_MAX_TRIFUNC 0x04 521 522 523 static struct { 524 tnl_points_func points; 525 tnl_line_func line; 526 tnl_triangle_func triangle; 527 tnl_quad_func quad; 528 } rast_tab[RADEON_MAX_TRIFUNC]; 529 530 531 #define DO_FALLBACK 0 532 #define DO_OFFSET 0 533 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT) 534 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT) 535 #define DO_FLAT 0 536 #define DO_TRI 1 537 #define DO_QUAD 1 538 #define DO_LINE 1 539 #define DO_POINTS 1 540 #define DO_FULL_QUAD 1 541 542 #define HAVE_SPEC 1 543 #define HAVE_BACK_COLORS 0 544 #define HAVE_HW_FLATSHADE 1 545 #define TAB rast_tab 546 547 #define DEPTH_SCALE 1.0 548 #define UNFILLED_TRI unfilled_tri 549 #define UNFILLED_QUAD unfilled_quad 550 #define VERT_X(_v) _v->v.x 551 #define VERT_Y(_v) _v->v.y 552 #define VERT_Z(_v) _v->v.z 553 #define AREA_IS_CCW( a ) (a < 0) 554 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int))) 555 556 #define VERT_SET_RGBA( v, c ) \ 557 do { \ 558 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \ 559 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ 560 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ 561 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ 562 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ 563 } while (0) 564 565 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] 566 567 #define VERT_SET_SPEC( v, c ) \ 568 do { \ 569 if (specoffset) { \ 570 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \ 571 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \ 572 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \ 573 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \ 574 } \ 575 } while (0) 576 #define VERT_COPY_SPEC( v0, v1 ) \ 577 do { \ 578 if (specoffset) { \ 579 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \ 580 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \ 581 spec0->red = spec1->red; \ 582 spec0->green = spec1->green; \ 583 spec0->blue = spec1->blue; \ 584 } \ 585 } while (0) 586 587 /* These don't need LE32_TO_CPU() as they used to save and restore 588 * colors which are already in the correct format. 589 */ 590 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] 591 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] 592 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] 593 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] 594 595 #undef LOCAL_VARS 596 #undef TAG 597 #undef INIT 598 599 #define LOCAL_VARS(n) \ 600 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 601 GLuint color[n] = {0}, spec[n] = {0}; \ 602 GLuint coloroffset = rmesa->swtcl.coloroffset; \ 603 GLuint specoffset = rmesa->swtcl.specoffset; \ 604 (void) color; (void) spec; (void) coloroffset; (void) specoffset; 605 606 /*********************************************************************** 607 * Helpers for rendering unfilled primitives * 608 ***********************************************************************/ 609 610 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] ) 611 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive 612 #undef TAG 613 #define TAG(x) x 614 #include "tnl_dd/t_dd_unfilled.h" 615 #undef IND 616 617 618 /*********************************************************************** 619 * Generate GL render functions * 620 ***********************************************************************/ 621 622 623 #define IND (0) 624 #define TAG(x) x 625 #include "tnl_dd/t_dd_tritmp.h" 626 627 #define IND (RADEON_TWOSIDE_BIT) 628 #define TAG(x) x##_twoside 629 #include "tnl_dd/t_dd_tritmp.h" 630 631 #define IND (RADEON_UNFILLED_BIT) 632 #define TAG(x) x##_unfilled 633 #include "tnl_dd/t_dd_tritmp.h" 634 635 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT) 636 #define TAG(x) x##_twoside_unfilled 637 #include "tnl_dd/t_dd_tritmp.h" 638 639 640 static void init_rast_tab( void ) 641 { 642 init(); 643 init_twoside(); 644 init_unfilled(); 645 init_twoside_unfilled(); 646 } 647 648 /**********************************************************************/ 649 /* Render unclipped begin/end objects */ 650 /**********************************************************************/ 651 652 #define RENDER_POINTS( start, count ) \ 653 for ( ; start < count ; start++) \ 654 radeon_point( rmesa, VERT(start) ) 655 #define RENDER_LINE( v0, v1 ) \ 656 radeon_line( rmesa, VERT(v0), VERT(v1) ) 657 #define RENDER_TRI( v0, v1, v2 ) \ 658 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) 659 #define RENDER_QUAD( v0, v1, v2, v3 ) \ 660 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) 661 #undef INIT 662 #define INIT(x) do { \ 663 radeonRenderPrimitive( ctx, x ); \ 664 } while (0) 665 #undef LOCAL_VARS 666 #define LOCAL_VARS \ 667 r100ContextPtr rmesa = R100_CONTEXT(ctx); \ 668 const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ 669 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \ 670 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ 671 const GLboolean stipple = ctx->Line.StippleFlag; \ 672 (void) elt; (void) stipple; 673 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx ); 674 #define RESET_OCCLUSION 675 #define PRESERVE_VB_DEFS 676 #define ELT(x) (x) 677 #define TAG(x) radeon_##x##_verts 678 #include "tnl/t_vb_rendertmp.h" 679 #undef ELT 680 #undef TAG 681 #define TAG(x) radeon_##x##_elts 682 #define ELT(x) elt[x] 683 #include "tnl/t_vb_rendertmp.h" 684 685 686 687 /**********************************************************************/ 688 /* Choose render functions */ 689 /**********************************************************************/ 690 691 void radeonChooseRenderState( struct gl_context *ctx ) 692 { 693 TNLcontext *tnl = TNL_CONTEXT(ctx); 694 r100ContextPtr rmesa = R100_CONTEXT(ctx); 695 GLuint index = 0; 696 GLuint flags = ctx->_TriangleCaps; 697 698 if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) 699 return; 700 701 if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT; 702 if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT; 703 704 if (index != rmesa->radeon.swtcl.RenderIndex) { 705 tnl->Driver.Render.Points = rast_tab[index].points; 706 tnl->Driver.Render.Line = rast_tab[index].line; 707 tnl->Driver.Render.ClippedLine = rast_tab[index].line; 708 tnl->Driver.Render.Triangle = rast_tab[index].triangle; 709 tnl->Driver.Render.Quad = rast_tab[index].quad; 710 711 if (index == 0) { 712 tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts; 713 tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts; 714 tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly; 715 } else { 716 tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; 717 tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; 718 tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; 719 } 720 721 rmesa->radeon.swtcl.RenderIndex = index; 722 } 723 } 724 725 726 /**********************************************************************/ 727 /* High level hooks for t_vb_render.c */ 728 /**********************************************************************/ 729 730 731 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim ) 732 { 733 r100ContextPtr rmesa = R100_CONTEXT(ctx); 734 735 if (rmesa->radeon.swtcl.hw_primitive != hwprim) { 736 RADEON_NEWPRIM( rmesa ); 737 rmesa->radeon.swtcl.hw_primitive = hwprim; 738 } 739 } 740 741 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim ) 742 { 743 r100ContextPtr rmesa = R100_CONTEXT(ctx); 744 rmesa->radeon.swtcl.render_primitive = prim; 745 if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED)) 746 radeonRasterPrimitive( ctx, reduced_hw_prim[prim] ); 747 } 748 749 static void radeonRenderFinish( struct gl_context *ctx ) 750 { 751 } 752 753 static void radeonResetLineStipple( struct gl_context *ctx ) 754 { 755 r100ContextPtr rmesa = R100_CONTEXT(ctx); 756 RADEON_STATECHANGE( rmesa, lin ); 757 } 758 759 760 /**********************************************************************/ 761 /* Transition to/from hardware rasterization. */ 762 /**********************************************************************/ 763 764 static const char * const fallbackStrings[] = { 765 "Texture mode", 766 "glDrawBuffer(GL_FRONT_AND_BACK)", 767 "glEnable(GL_STENCIL) without hw stencil buffer", 768 "glRenderMode(selection or feedback)", 769 "glBlendEquation", 770 "glBlendFunc", 771 "RADEON_NO_RAST", 772 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)" 773 }; 774 775 776 static const char *getFallbackString(GLuint bit) 777 { 778 int i = 0; 779 while (bit > 1) { 780 i++; 781 bit >>= 1; 782 } 783 return fallbackStrings[i]; 784 } 785 786 787 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode ) 788 { 789 r100ContextPtr rmesa = R100_CONTEXT(ctx); 790 TNLcontext *tnl = TNL_CONTEXT(ctx); 791 GLuint oldfallback = rmesa->radeon.Fallback; 792 793 if (mode) { 794 rmesa->radeon.Fallback |= bit; 795 if (oldfallback == 0) { 796 radeon_firevertices(&rmesa->radeon); 797 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE ); 798 _swsetup_Wakeup( ctx ); 799 rmesa->radeon.swtcl.RenderIndex = ~0; 800 if (RADEON_DEBUG & RADEON_FALLBACKS) { 801 fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n", 802 bit, getFallbackString(bit)); 803 } 804 } 805 } 806 else { 807 rmesa->radeon.Fallback &= ~bit; 808 if (oldfallback == bit) { 809 _swrast_flush( ctx ); 810 tnl->Driver.Render.Start = radeonRenderStart; 811 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive; 812 tnl->Driver.Render.Finish = radeonRenderFinish; 813 814 tnl->Driver.Render.BuildVertices = _tnl_build_vertices; 815 tnl->Driver.Render.CopyPV = _tnl_copy_pv; 816 tnl->Driver.Render.Interp = _tnl_interp; 817 818 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple; 819 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE ); 820 if (rmesa->radeon.TclFallback) { 821 /* These are already done if rmesa->radeon.TclFallback goes to 822 * zero above. But not if it doesn't (RADEON_NO_TCL for 823 * example?) 824 */ 825 _tnl_invalidate_vertex_state( ctx, ~0 ); 826 _tnl_invalidate_vertices( ctx, ~0 ); 827 rmesa->radeon.tnl_index_bitset = 0; 828 radeonChooseVertexState( ctx ); 829 radeonChooseRenderState( ctx ); 830 } 831 if (RADEON_DEBUG & RADEON_FALLBACKS) { 832 fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n", 833 bit, getFallbackString(bit)); 834 } 835 } 836 } 837 } 838 839 840 /**********************************************************************/ 841 /* Initialization. */ 842 /**********************************************************************/ 843 844 void radeonInitSwtcl( struct gl_context *ctx ) 845 { 846 TNLcontext *tnl = TNL_CONTEXT(ctx); 847 r100ContextPtr rmesa = R100_CONTEXT(ctx); 848 static int firsttime = 1; 849 850 if (firsttime) { 851 init_rast_tab(); 852 firsttime = 0; 853 } 854 rmesa->radeon.swtcl.emit_prediction = 0; 855 856 tnl->Driver.Render.Start = radeonRenderStart; 857 tnl->Driver.Render.Finish = radeonRenderFinish; 858 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive; 859 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple; 860 tnl->Driver.Render.BuildVertices = _tnl_build_vertices; 861 tnl->Driver.Render.CopyPV = _tnl_copy_pv; 862 tnl->Driver.Render.Interp = _tnl_interp; 863 864 _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 865 RADEON_MAX_TNL_VERTEX_SIZE); 866 867 rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; 868 rmesa->radeon.swtcl.RenderIndex = ~0; 869 rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; 870 rmesa->radeon.swtcl.hw_primitive = 0; 871 } 872 873
