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      1 // Copyright 2015, ARM Limited
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_FCVTNS_XS_TRACE_A64_H_
     35 #define VIXL_SIM_FCVTNS_XS_TRACE_A64_H_
     36 
     37 const int64_t kExpected_fcvtns_xs[] = {
     38   INT64_C(0),
     39   INT64_C(0),
     40   INT64_C(0),
     41   INT64_C(0),
     42   INT64_C(1),
     43   INT64_C(1),
     44   INT64_C(1),
     45   INT64_C(1),
     46   INT64_C(2),
     47   INT64_C(10),
     48   INT64_C(0),
     49   INT64_C(9223372036854775807),
     50   INT64_C(0),
     51   INT64_C(0),
     52   INT64_C(0),
     53   INT64_C(0),
     54   INT64_C(0),
     55   INT64_C(0),
     56   INT64_C(0),
     57   INT64_C(0),
     58   INT64_C(0),
     59   INT64_C(0),
     60   INT64_C(0),
     61   -INT64_C(1),
     62   -INT64_C(1),
     63   -INT64_C(1),
     64   -INT64_C(1),
     65   -INT64_C(2),
     66   -INT64_C(10),
     67   INT64_C(0),
     68   -INT64_C(9223372036854775807) - 1,
     69   INT64_C(0),
     70   INT64_C(0),
     71   INT64_C(0),
     72   INT64_C(0),
     73   INT64_C(0),
     74   INT64_C(0),
     75   INT64_C(0),
     76   INT64_C(8388608),
     77   INT64_C(8388609),
     78   INT64_C(8388610),
     79   INT64_C(8388611),
     80   INT64_C(16143410),
     81   INT64_C(16777212),
     82   INT64_C(16777213),
     83   INT64_C(16777214),
     84   INT64_C(16777215),
     85   INT64_C(4194304),
     86   INT64_C(4194304),
     87   INT64_C(4194305),
     88   INT64_C(4194306),
     89   INT64_C(8071705),
     90   INT64_C(8388606),
     91   INT64_C(8388606),
     92   INT64_C(8388607),
     93   INT64_C(8388608),
     94   INT64_C(2097152),
     95   INT64_C(2097152),
     96   INT64_C(2097152),
     97   INT64_C(2097153),
     98   INT64_C(4035852),
     99   INT64_C(4194303),
    100   INT64_C(4194303),
    101   INT64_C(4194304),
    102   INT64_C(4194304),
    103   -INT64_C(8388608),
    104   -INT64_C(8388609),
    105   -INT64_C(8388610),
    106   -INT64_C(8388611),
    107   -INT64_C(16143410),
    108   -INT64_C(16777212),
    109   -INT64_C(16777213),
    110   -INT64_C(16777214),
    111   -INT64_C(16777215),
    112   -INT64_C(4194304),
    113   -INT64_C(4194304),
    114   -INT64_C(4194305),
    115   -INT64_C(4194306),
    116   -INT64_C(8071705),
    117   -INT64_C(8388606),
    118   -INT64_C(8388606),
    119   -INT64_C(8388607),
    120   -INT64_C(8388608),
    121   -INT64_C(2097152),
    122   -INT64_C(2097152),
    123   -INT64_C(2097152),
    124   -INT64_C(2097153),
    125   -INT64_C(4035852),
    126   -INT64_C(4194303),
    127   -INT64_C(4194303),
    128   -INT64_C(4194304),
    129   -INT64_C(4194304),
    130   -INT64_C(9223372036854775807) - 1,
    131   -INT64_C(9223372036854775807) - 1,
    132   -INT64_C(9223371487098961920),
    133   INT64_C(9223371487098961920),
    134   INT64_C(9223372036854775807),
    135   INT64_C(9223372036854775807),
    136   INT64_C(9223372036854775807),
    137   -INT64_C(2147483904),
    138   -INT64_C(2147483648),
    139   -INT64_C(2147483520),
    140   INT64_C(2147483520),
    141   INT64_C(2147483648),
    142 };
    143 const unsigned kExpectedCount_fcvtns_xs = 104;
    144 
    145 #endif  // VIXL_SIM_FCVTNS_XS_TRACE_A64_H_
    146