1 @/* 2 @ ** Copyright 2003-2010, VisualOn, Inc. 3 @ ** 4 @ ** Licensed under the Apache License, Version 2.0 (the "License"); 5 @ ** you may not use this file except in compliance with the License. 6 @ ** You may obtain a copy of the License at 7 @ ** 8 @ ** http://www.apache.org/licenses/LICENSE-2.0 9 @ ** 10 @ ** Unless required by applicable law or agreed to in writing, software 11 @ ** distributed under the License is distributed on an "AS IS" BASIS, 12 @ ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 @ ** See the License for the specific language governing permissions and 14 @ ** limitations under the License. 15 @ */ 16 @ 17 @void Deemph_32( 18 @ Word16 x_hi[], /* (i) : input signal (bit31..16) */ 19 @ Word16 x_lo[], /* (i) : input signal (bit15..4) */ 20 @ Word16 y[], /* (o) : output signal (x16) */ 21 @ Word16 mu, /* (i) Q15 : deemphasis factor */ 22 @ Word16 L, /* (i) : vector size */ 23 @ Word16 * mem /* (i/o) : memory (y[-1]) */ 24 @ ) 25 26 @x_hi RN R0 27 @x_lo RN R1 28 @y[] RN R2 29 @*mem RN R3 30 31 .section .text 32 .global Deemph_32_asm 33 34 Deemph_32_asm: 35 36 STMFD r13!, {r4 - r12, r14} 37 MOV r4, #2 @i=0 38 LDRSH r6, [r0], #2 @load x_hi[0] 39 LDRSH r7, [r1], #2 @load x_lo[0] 40 LDR r5, =22282 @r5---mu 41 MOV r11, #0x8000 42 43 @y[0] 44 MOV r10, r6, LSL #16 @L_tmp = x_hi[0]<<16 45 MOV r8, r5, ASR #1 @fac = mu >> 1 46 LDR r5, [r3] 47 ADD r12, r10, r7, LSL #4 @L_tmp += x_lo[0] << 4 48 MOV r10, r12, LSL #3 @L_tmp <<= 3 49 MUL r9, r5, r8 50 LDRSH r6, [r0], #2 @load x_hi[1] 51 QDADD r10, r10, r9 52 LDRSH r7, [r1], #2 @load x_lo[1] 53 MOV r12, r10, LSL #1 @L_tmp = L_mac(L_tmp, *mem, fac) 54 QADD r10, r12, r11 55 MOV r14, r10, ASR #16 @y[0] = round(L_tmp) 56 57 58 MOV r10, r6, LSL #16 59 ADD r12, r10, r7, LSL #4 60 STRH r14, [r2], #2 @update y[0] 61 MOV r10, r12, LSL #3 62 MUL r9, r14, r8 63 QDADD r10, r10, r9 64 MOV r12, r10, LSL #1 65 QADD r10, r12, r11 66 MOV r14, r10, ASR #16 @y[1] = round(L_tmp) 67 68 LOOP: 69 LDRSH r6, [r0], #2 @load x_hi[] 70 LDRSH r7, [r1], #2 71 STRH r14, [r2], #2 72 MOV r10, r6, LSL #16 73 ADD r12, r10, r7, LSL #4 74 MUL r9, r14, r8 75 MOV r10, r12, LSL #3 76 QDADD r10, r10, r9 77 LDRSH r6, [r0], #2 @load x_hi[] 78 MOV r12, r10, LSL #1 79 QADD r10, r12, r11 80 LDRSH r7, [r1], #2 81 MOV r14, r10, ASR #16 82 83 MOV r10, r6, LSL #16 84 ADD r12, r10, r7, LSL #4 85 STRH r14, [r2], #2 86 MUL r9, r14, r8 87 MOV r10, r12, LSL #3 88 QDADD r10, r10, r9 89 ADD r4, r4, #2 90 MOV r12, r10, LSL #1 91 QADD r10, r12, r11 92 CMP r4, #64 93 MOV r14, r10, ASR #16 94 95 BLT LOOP 96 STR r14, [r3] 97 STRH r14, [r2] 98 99 LDMFD r13!, {r4 - r12, r15} 100 101 .END 102 103
