1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27 /* Register CR_IMG_MVEA_SRST */ 28 #define MVEA_CR_IMG_MVEA_SRST 0x0000 29 #define MASK_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x00000001 30 #define SHIFT_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0 31 #define REGNUM_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x0000 32 33 #define MASK_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x00000002 34 #define SHIFT_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 1 35 #define REGNUM_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x0000 36 37 #define MASK_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x00000004 38 #define SHIFT_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 2 39 #define REGNUM_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x0000 40 41 #define MASK_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x00000008 42 #define SHIFT_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 3 43 #define REGNUM_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x0000 44 45 #define MASK_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x00000010 46 #define SHIFT_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 4 47 #define REGNUM_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x0000 48 49 #define MASK_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x00000020 50 #define SHIFT_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 5 51 #define REGNUM_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x0000 52 53 /* Register CR_IMG_MVEA_INTSTAT */ 54 #define MVEA_CR_IMG_MVEA_INTSTAT 0x0004 55 #define MASK_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0x00000001 56 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0 57 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SPE_DONE 0x0004 58 59 #define MASK_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 0x00000002 60 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 1 61 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_IPE_DONE 0x0004 62 63 #define MASK_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 0x00000004 64 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 2 65 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_CMPRS_DONE 0x0004 66 67 #define MASK_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 0x00000008 68 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 3 69 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_JMCOMP_DONE 0x0004 70 71 #define MASK_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 0x00000010 72 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 4 73 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_EDMA_DONE 0x0004 74 75 #define MASK_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 0x00000020 76 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 5 77 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_TDMA_DONE 0x0004 78 79 #define MASK_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 0x00000040 80 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 6 81 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_DEB_DONE 0x0004 82 83 #define MASK_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 0x00000080 84 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 7 85 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_VLC_DONE 0x0004 86 87 #define MASK_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 0x00000100 88 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 8 89 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SOFTWARE0 0x0004 90 91 #define MASK_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 0x00000200 92 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 9 93 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SOFTWARE1 0x0004 94 95 #define MASK_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 0x00000400 96 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 10 97 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_DCF_EMPTY 0x0004 98 99 #define MASK_MVEA_CR_IMG_MVEA_INTS_SEQ_START 0x00000800 100 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SEQ_START 11 101 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SEQ_START 0x0004 102 103 #define MASK_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 0x00001000 104 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 12 105 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_SEQ_DONE 0x0004 106 107 #define MASK_MVEA_CR_IMG_MVEA_INTS_COMBINED 0x40000000 108 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_COMBINED 30 109 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_COMBINED 0x0004 110 111 #define MASK_MVEA_CR_IMG_MVEA_INTS_MASTER 0x80000000 112 #define SHIFT_MVEA_CR_IMG_MVEA_INTS_MASTER 31 113 #define REGNUM_MVEA_CR_IMG_MVEA_INTS_MASTER 0x0004 114 115 /* Register CR_IMG_MVEA_INTENAB */ 116 #define MVEA_CR_IMG_MVEA_INTENAB 0x0008 117 #define MASK_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0x00000001 118 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0 119 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SPE_DONE 0x0008 120 121 #define MASK_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 0x00000002 122 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 1 123 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_IPE_DONE 0x0008 124 125 #define MASK_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 0x00000004 126 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 2 127 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_CMPRS_DONE 0x0008 128 129 #define MASK_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 0x00000008 130 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 3 131 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_JMCOMP_DONE 0x0008 132 133 #define MASK_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 0x00000010 134 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 4 135 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_EDMA_DONE 0x0008 136 137 #define MASK_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 0x00000020 138 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 5 139 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_TDMA_DONE 0x0008 140 141 #define MASK_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 0x00000040 142 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 6 143 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_DEB_DONE 0x0008 144 145 #define MASK_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 0x00000080 146 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 7 147 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_VLC_DONE 0x0008 148 149 #define MASK_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 0x00000100 150 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 8 151 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE0 0x0008 152 153 #define MASK_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 0x00000200 154 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 9 155 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SOFTWARE1 0x0008 156 157 #define MASK_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 0x00000400 158 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 10 159 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_DCF_EMPTY 0x0008 160 161 #define MASK_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 0x00000800 162 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 11 163 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SEQ_START 0x0008 164 165 #define MASK_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 0x00001000 166 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 12 167 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_SEQ_DONE 0x0008 168 169 #define MASK_MVEA_CR_IMG_MVEA_INTEN_COMBINED 0x40000000 170 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_COMBINED 30 171 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_COMBINED 0x0008 172 173 #define MASK_MVEA_CR_IMG_MVEA_INTEN_MASTER 0x80000000 174 #define SHIFT_MVEA_CR_IMG_MVEA_INTEN_MASTER 31 175 #define REGNUM_MVEA_CR_IMG_MVEA_INTEN_MASTER 0x0008 176 177 /* Register CR_IMG_MVEA_INTCLEAR */ 178 #define MVEA_CR_IMG_MVEA_INTCLEAR 0x000C 179 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0x00000001 180 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0 181 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SPE_DONE 0x000C 182 183 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 0x00000002 184 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 1 185 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_IPE_DONE 0x000C 186 187 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 0x00000004 188 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 2 189 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_CMPRS_DONE 0x000C 190 191 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 0x00000008 192 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 3 193 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_JMCOMP_DONE 0x000C 194 195 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 0x00000010 196 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 4 197 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_EDMA_DONE 0x000C 198 199 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 0x00000020 200 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 5 201 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_TDMA_DONE 0x000C 202 203 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 0x00000040 204 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 6 205 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_DEB_DONE 0x000C 206 207 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 0x00000080 208 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 7 209 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_VLC_DONE 0x000C 210 211 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 0x00000100 212 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 8 213 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE0 0x000C 214 215 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 0x00000200 216 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 9 217 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SOFTWARE1 0x000C 218 219 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 0x00000400 220 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 10 221 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_DCF_EMPTY 0x000C 222 223 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 0x00000800 224 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 11 225 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SEQ_START 0x000C 226 227 #define MASK_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 0x00001000 228 #define SHIFT_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 12 229 #define REGNUM_MVEA_CR_IMG_MVEA_INTCLR_SEQ_DONE 0x000C 230 231 /* Register CR_IMG_MVEA_INT_COMB_SEL */ 232 #define MVEA_CR_IMG_MVEA_INT_COMB_SEL 0x0010 233 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0x00000001 234 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0 235 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SPE_DONE 0x0010 236 237 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 0x00000002 238 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 1 239 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_IPE_DONE 0x0010 240 241 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 0x00000004 242 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 2 243 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_CMPRS_DONE 0x0010 244 245 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 0x00000008 246 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 3 247 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_JMCOMP_DONE 0x0010 248 249 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 0x00000010 250 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 4 251 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_EDMA_DONE 0x0010 252 253 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 0x00000020 254 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 5 255 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_TDMA_DONE 0x0010 256 257 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 0x00000040 258 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 6 259 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_DEB_DONE 0x0010 260 261 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 0x00000080 262 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 7 263 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_VLC_DONE 0x0010 264 265 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 0x00000100 266 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 8 267 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE0 0x0010 268 269 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 0x00000200 270 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 9 271 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SOFTWARE1 0x0010 272 273 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 0x00000400 274 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 10 275 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_DCF_EMPTY 0x0010 276 277 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 0x00000800 278 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 11 279 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_START 0x0010 280 281 #define MASK_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 0x00001000 282 #define SHIFT_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 12 283 #define REGNUM_MVEA_CR_IMG_MVEA_INTCSEL_SEQ_DONE 0x0010 284 285 /* Register CR_MVEA_START */ 286 #define MVEA_CR_MVEA_START 0x0014 287 #define MASK_MVEA_CR_MVEA_SPE_START 0x00000001 288 #define SHIFT_MVEA_CR_MVEA_SPE_START 0 289 #define REGNUM_MVEA_CR_MVEA_SPE_START 0x0014 290 291 #define MASK_MVEA_CR_MVEA_IPE_START 0x00000002 292 #define SHIFT_MVEA_CR_MVEA_IPE_START 1 293 #define REGNUM_MVEA_CR_MVEA_IPE_START 0x0014 294 295 #define MASK_MVEA_CR_MVEA_CMPRS_START 0x00000004 296 #define SHIFT_MVEA_CR_MVEA_CMPRS_START 2 297 #define REGNUM_MVEA_CR_MVEA_CMPRS_START 0x0014 298 299 #define MASK_MVEA_CR_MVEA_JMCOMP_START 0x00000008 300 #define SHIFT_MVEA_CR_MVEA_JMCOMP_START 3 301 #define REGNUM_MVEA_CR_MVEA_JMCOMP_START 0x0014 302 303 #define MASK_MVEA_CR_MVEA_DEB_START 0x00000040 304 #define SHIFT_MVEA_CR_MVEA_DEB_START 6 305 #define REGNUM_MVEA_CR_MVEA_DEB_START 0x0014 306 307 #define MASK_MVEA_CR_MVEA_VLC_START 0x00000080 308 #define SHIFT_MVEA_CR_MVEA_VLC_START 7 309 #define REGNUM_MVEA_CR_MVEA_VLC_START 0x0014 310 311 /* Register CR_MVEA_BUSY */ 312 #define MVEA_CR_MVEA_BUSY 0x0018 313 #define MASK_MVEA_CR_MVEA_SPE_BUSY 0x00000001 314 #define SHIFT_MVEA_CR_MVEA_SPE_BUSY 0 315 #define REGNUM_MVEA_CR_MVEA_SPE_BUSY 0x0018 316 317 #define MASK_MVEA_CR_MVEA_IPE_BUSY 0x00000002 318 #define SHIFT_MVEA_CR_MVEA_IPE_BUSY 1 319 #define REGNUM_MVEA_CR_MVEA_IPE_BUSY 0x0018 320 321 #define MASK_MVEA_CR_MVEA_CMPRS_BUSY 0x00000004 322 #define SHIFT_MVEA_CR_MVEA_CMPRS_BUSY 2 323 #define REGNUM_MVEA_CR_MVEA_CMPRS_BUSY 0x0018 324 325 #define MASK_MVEA_CR_MVEA_JMCOMP_BUSY 0x00000008 326 #define SHIFT_MVEA_CR_MVEA_JMCOMP_BUSY 3 327 #define REGNUM_MVEA_CR_MVEA_JMCOMP_BUSY 0x0018 328 329 #define MASK_MVEA_CR_MVEA_EDMA_BUSY 0x00000010 330 #define SHIFT_MVEA_CR_MVEA_EDMA_BUSY 4 331 #define REGNUM_MVEA_CR_MVEA_EDMA_BUSY 0x0018 332 333 #define MASK_MVEA_CR_MVEA_TDMA_BUSY 0x00000020 334 #define SHIFT_MVEA_CR_MVEA_TDMA_BUSY 5 335 #define REGNUM_MVEA_CR_MVEA_TDMA_BUSY 0x0018 336 337 #define MASK_MVEA_CR_MVEA_DEB_BUSY 0x00000040 338 #define SHIFT_MVEA_CR_MVEA_DEB_BUSY 6 339 #define REGNUM_MVEA_CR_MVEA_DEB_BUSY 0x0018 340 341 #define MASK_MVEA_CR_MVEA_VLC_BUSY 0x00000080 342 #define SHIFT_MVEA_CR_MVEA_VLC_BUSY 7 343 #define REGNUM_MVEA_CR_MVEA_VLC_BUSY 0x0018 344 345 #define MASK_MVEA_CR_MVEA_SPE_LRB_BUSY 0x00000100 346 #define SHIFT_MVEA_CR_MVEA_SPE_LRB_BUSY 8 347 #define REGNUM_MVEA_CR_MVEA_SPE_LRB_BUSY 0x0018 348 349 /* Register CR_MVEA_DMACMDFIFO_WAIT */ 350 #define MVEA_CR_MVEA_DMACMDFIFO_WAIT 0x001C 351 #define MASK_MVEA_CR_MVEA_DCF_WAIT_SPE 0x00000001 352 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SPE 0 353 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SPE 0x001C 354 355 #define MASK_MVEA_CR_MVEA_DCF_WAIT_IPE 0x00000002 356 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_IPE 1 357 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_IPE 0x001C 358 359 #define MASK_MVEA_CR_MVEA_DCF_WAIT_CMPRS 0x00000004 360 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_CMPRS 2 361 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_CMPRS 0x001C 362 363 #define MASK_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 0x00000008 364 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 3 365 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_JMCOMP 0x001C 366 367 #define MASK_MVEA_CR_MVEA_DCF_WAIT_EDMA 0x00000010 368 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_EDMA 4 369 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_EDMA 0x001C 370 371 #define MASK_MVEA_CR_MVEA_DCF_WAIT_TDMA 0x00000020 372 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_TDMA 5 373 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_TDMA 0x001C 374 375 #define MASK_MVEA_CR_MVEA_DCF_WAIT_SW0 0x00000040 376 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SW0 6 377 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SW0 0x001C 378 379 #define MASK_MVEA_CR_MVEA_DCF_WAIT_SW1 0x00000080 380 #define SHIFT_MVEA_CR_MVEA_DCF_WAIT_SW1 7 381 #define REGNUM_MVEA_CR_MVEA_DCF_WAIT_SW1 0x001C 382 383 /* Register CR_MVEA_DMACMDFIFO_STATUS */ 384 #define MVEA_CR_MVEA_DMACMDFIFO_STATUS 0x0020 385 #define MASK_MVEA_CR_MVEA_DCF_SPACE 0x0000001F 386 #define SHIFT_MVEA_CR_MVEA_DCF_SPACE 0 387 #define REGNUM_MVEA_CR_MVEA_DCF_SPACE 0x0020 388 389 #define MASK_MVEA_CR_MVEA_DCF_EMPTY 0x00000100 390 #define SHIFT_MVEA_CR_MVEA_DCF_EMPTY 8 391 #define REGNUM_MVEA_CR_MVEA_DCF_EMPTY 0x0020 392 393 /* Register CR_MVEA_AUTO_CLOCK_GATING */ 394 #define MVEA_CR_MVEA_AUTO_CLOCK_GATING 0x0024 395 #define MASK_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x00000001 396 #define SHIFT_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0 397 #define REGNUM_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x0024 398 399 #define MASK_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x00000002 400 #define SHIFT_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 1 401 #define REGNUM_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x0024 402 403 #define MASK_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x00000004 404 #define SHIFT_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 2 405 #define REGNUM_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x0024 406 407 #define MASK_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x00000008 408 #define SHIFT_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 3 409 #define REGNUM_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x0024 410 411 /* Register CR_MVEA_MAN_CLOCK_GATING */ 412 #define MVEA_CR_MVEA_MAN_CLOCK_GATING 0x0028 413 #define MASK_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0x00000001 414 #define SHIFT_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0 415 #define REGNUM_MVEA_CR_MVEA_SPE_MAN_CLK_GATE 0x0028 416 417 #define MASK_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 0x00000002 418 #define SHIFT_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 1 419 #define REGNUM_MVEA_CR_MVEA_IPE_MAN_CLK_GATE 0x0028 420 421 #define MASK_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 0x00000004 422 #define SHIFT_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 2 423 #define REGNUM_MVEA_CR_MVEA_CMPRS_MAN_CLK_GATE 0x0028 424 425 #define MASK_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 0x00000008 426 #define SHIFT_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 3 427 #define REGNUM_MVEA_CR_MVEA_JMCOMP_MAN_CLK_GATE 0x0028 428 429 #define MASK_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 0x00000010 430 #define SHIFT_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 4 431 #define REGNUM_MVEA_CR_MVEA_CMC_MAN_CLK_GATE 0x0028 432 433 /* Register CR_TOPAZ_MB_PERFORMANCE_RESULT */ 434 #define MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x002C 435 #define MASK_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x0000FFFF 436 #define SHIFT_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0 437 #define REGNUM_MVEA_CR_TOPAZ_MB_PERFORMANCE_RESULT 0x002C 438 439 /* Register CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER */ 440 #define MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x0030 441 #define MASK_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF 442 #define SHIFT_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0 443 #define REGNUM_MVEA_CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER 0x0030 444 445 /* Register CR_TOPAZ_HW_MB_PERFORMANCE_RESULT */ 446 #define MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0034 447 #define MASK_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0000FFFF 448 #define SHIFT_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0 449 #define REGNUM_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_RESULT 0x0034 450 451 /* Register CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER */ 452 #define MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x0038 453 #define MASK_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF 454 #define SHIFT_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0 455 #define REGNUM_MVEA_CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER 0x0038 456 457 /* Register CR_CMC_ESB_DIAGNOSTICS */ 458 #define MVEA_CR_CMC_ESB_DIAGNOSTICS 0x0100 459 #define MASK_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0xFFFFFFFF 460 #define SHIFT_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0 461 #define REGNUM_MVEA_CR_CMC_ESB_DIAGNOSTICS1 0x0100 462 463 /* Register CR_CMC_DMA_DIAGNOSTICS */ 464 #define MVEA_CR_CMC_DMA_DIAGNOSTICS 0x0104 465 #define MASK_MVEA_CR_CMC_DMA_DIAGNOSTICS 0xFFFFFFFF 466 #define SHIFT_MVEA_CR_CMC_DMA_DIAGNOSTICS 0 467 #define REGNUM_MVEA_CR_CMC_DMA_DIAGNOSTICS 0x0104 468 469 /* Register CR_CMC_SIGNATURE_ENC_MEM_WDATA */ 470 #define MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0x0108 471 #define MASK_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0xFFFFFFFF 472 #define SHIFT_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0 473 #define REGNUM_MVEA_CR_CMC_SIGNATURE_ENC_MEM_WDATA 0x0108 474 475 /* Register CR_CMC_SIGNATURE_ENC_MEM_ADDR */ 476 #define MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0x010C 477 #define MASK_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0xFFFFFFFF 478 #define SHIFT_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0 479 #define REGNUM_MVEA_CR_CMC_SIGNATURE_ENC_MEM_ADDR 0x010C 480 481 /* Register CR_CMC_PROC_ESB_ACCESS */ 482 #define MVEA_CR_CMC_PROC_ESB_ACCESS 0x011C 483 #define MASK_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0x0000001F 484 #define SHIFT_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0 485 #define REGNUM_MVEA_CR_CMC_PROC_ESB_REGION_NUMBER 0x011C 486 487 /* Register CR_CMC_LRB_LOGICAL_OFFSET */ 488 #define MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x012C 489 #define MASK_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x0000001F 490 #define SHIFT_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0 491 #define REGNUM_MVEA_CR_CMC_LRB_LOGICAL_OFFSET 0x012C 492 493 /* Register CR_SEQUENCER_SETUP */ 494 #define MVEA_CR_SEQUENCER_SETUP 0x0130 495 #define MASK_MVEA_CR_FIRMWARE_DONE 0x00000001 496 #define SHIFT_MVEA_CR_FIRMWARE_DONE 0 497 #define REGNUM_MVEA_CR_FIRMWARE_DONE 0x0130 498 499 #define MASK_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 0x00000010 500 #define SHIFT_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 4 501 #define REGNUM_MVEA_CR_FIRMWARE_ROW_SETUP_DONE 0x0130 502 503 #define MASK_MVEA_CR_CONTROL_UPDATE 0x00000100 504 #define SHIFT_MVEA_CR_CONTROL_UPDATE 8 505 #define REGNUM_MVEA_CR_CONTROL_UPDATE 0x0130 506 507 #define MASK_MVEA_CR_STATUS_UPDATE 0x00001000 508 #define SHIFT_MVEA_CR_STATUS_UPDATE 12 509 #define REGNUM_MVEA_CR_STATUS_UPDATE 0x0130 510 511 /* Register CR_SEQUENCER_CONTROL */ 512 #define MVEA_CR_SEQUENCER_CONTROL 0x0134 513 #define MASK_MVEA_CR_IPE_ENABLE 0x00000001 514 #define SHIFT_MVEA_CR_IPE_ENABLE 0 515 #define REGNUM_MVEA_CR_IPE_ENABLE 0x0134 516 517 #define MASK_MVEA_CR_SPE_ENABLE 0x00000002 518 #define SHIFT_MVEA_CR_SPE_ENABLE 1 519 #define REGNUM_MVEA_CR_SPE_ENABLE 0x0134 520 521 #define MASK_MVEA_CR_CMPRS_ENABLE 0x00000004 522 #define SHIFT_MVEA_CR_CMPRS_ENABLE 2 523 #define REGNUM_MVEA_CR_CMPRS_ENABLE 0x0134 524 525 #define MASK_MVEA_CR_JMCOMP_ENABLE 0x00000008 526 #define SHIFT_MVEA_CR_JMCOMP_ENABLE 3 527 #define REGNUM_MVEA_CR_JMCOMP_ENABLE 0x0134 528 529 #define MASK_MVEA_CR_VLC_ENABLE 0x00000010 530 #define SHIFT_MVEA_CR_VLC_ENABLE 4 531 #define REGNUM_MVEA_CR_VLC_ENABLE 0x0134 532 533 #define MASK_MVEA_CR_DB_ENABLE 0x00000020 534 #define SHIFT_MVEA_CR_DB_ENABLE 5 535 #define REGNUM_MVEA_CR_DB_ENABLE 0x0134 536 537 #define MASK_MVEA_CR_DMA_ABOVE_PIX_IN_EN 0x00000100 538 #define SHIFT_MVEA_CR_DMA_ABOVE_PIX_IN_EN 8 539 #define REGNUM_MVEA_CR_DMA_ABOVE_PIX_IN_EN 0x0134 540 541 #define MASK_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 0x00000200 542 #define SHIFT_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 9 543 #define REGNUM_MVEA_CR_DMA_ABOVE_PIX_OUT_EN 0x0134 544 545 #define MASK_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 0x00000400 546 #define SHIFT_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 10 547 #define REGNUM_MVEA_CR_DMA_ABOVE_PARAMS_IN_EN 0x0134 548 549 #define MASK_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 0x00000800 550 #define SHIFT_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 11 551 #define REGNUM_MVEA_CR_DMA_ABOVE_PARAMS_OUT_EN 0x0134 552 553 #define MASK_MVEA_CR_DMA_CURR_MB_IN_EN 0x00001000 554 #define SHIFT_MVEA_CR_DMA_CURR_MB_IN_EN 12 555 #define REGNUM_MVEA_CR_DMA_CURR_MB_IN_EN 0x0134 556 557 #define MASK_MVEA_CR_DMA_RECON_OUT_EN 0x00002000 558 #define SHIFT_MVEA_CR_DMA_RECON_OUT_EN 13 559 #define REGNUM_MVEA_CR_DMA_RECON_OUT_EN 0x0134 560 561 #define MASK_MVEA_CR_DMA_BELOW_OUT_EN 0x00004000 562 #define SHIFT_MVEA_CR_DMA_BELOW_OUT_EN 14 563 #define REGNUM_MVEA_CR_DMA_BELOW_OUT_EN 0x0134 564 565 #define MASK_MVEA_CR_DMA_BELOW1_IN_EN 0x00008000 566 #define SHIFT_MVEA_CR_DMA_BELOW1_IN_EN 15 567 #define REGNUM_MVEA_CR_DMA_BELOW1_IN_EN 0x0134 568 569 #define MASK_MVEA_CR_DMA_BELOW2_IN_EN 0x00010000 570 #define SHIFT_MVEA_CR_DMA_BELOW2_IN_EN 16 571 #define REGNUM_MVEA_CR_DMA_BELOW2_IN_EN 0x0134 572 573 #define MASK_MVEA_CR_DMA_CURR_PARAMS_IN_EN 0x00020000 574 #define SHIFT_MVEA_CR_DMA_CURR_PARAMS_IN_EN 17 575 #define REGNUM_MVEA_CR_DMA_CURR_PARAMS_IN_EN 0x0134 576 577 #define MASK_MVEA_CR_DMA_LRB0 0x00040000 578 #define SHIFT_MVEA_CR_DMA_LRB0 18 579 #define REGNUM_MVEA_CR_DMA_LRB0 0x0134 580 581 #define MASK_MVEA_CR_DMA_LRB1 0x00080000 582 #define SHIFT_MVEA_CR_DMA_LRB1 19 583 #define REGNUM_MVEA_CR_DMA_LRB1 0x0134 584 585 #define MASK_MVEA_CR_MB_NO_PER_ROW 0x0FF00000 586 #define SHIFT_MVEA_CR_MB_NO_PER_ROW 20 587 #define REGNUM_MVEA_CR_MB_NO_PER_ROW 0x0134 588 589 #define MASK_MVEA_CR_CURR_UV_INTERLEAVED 0x10000000 590 #define SHIFT_MVEA_CR_CURR_UV_INTERLEAVED 28 591 #define REGNUM_MVEA_CR_CURR_UV_INTERLEAVED 0x0134 592 593 #define MASK_MVEA_CR_START_OF_SLICE 0x20000000 594 #define SHIFT_MVEA_CR_START_OF_SLICE 29 595 #define REGNUM_MVEA_CR_START_OF_SLICE 0x0134 596 597 #define MASK_MVEA_CR_DB_FLUSH 0x40000000 598 #define SHIFT_MVEA_CR_DB_FLUSH 30 599 #define REGNUM_MVEA_CR_DB_FLUSH 0x0134 600 601 #define MASK_MVEA_CR_SEQUENCER_ENABLE 0x80000000 602 #define SHIFT_MVEA_CR_SEQUENCER_ENABLE 31 603 #define REGNUM_MVEA_CR_SEQUENCER_ENABLE 0x0134 604 605 /* Register CR_CURR_MB_Y_ROW_ADDR */ 606 #define MVEA_CR_CURR_MB_Y_ROW_ADDR 0x0138 607 #define MASK_MVEA_CR_CURR_MB_Y_ROW_ADDR 0xFFFFFFFF 608 #define SHIFT_MVEA_CR_CURR_MB_Y_ROW_ADDR 0 609 #define REGNUM_MVEA_CR_CURR_MB_Y_ROW_ADDR 0x0138 610 611 /* Register CR_CURR_MB_U_ROW_ADDR */ 612 #define MVEA_CR_CURR_MB_U_ROW_ADDR 0x013C 613 #define MASK_MVEA_CR_CURR_MB_U_ROW_ADDR 0xFFFFFFFF 614 #define SHIFT_MVEA_CR_CURR_MB_U_ROW_ADDR 0 615 #define REGNUM_MVEA_CR_CURR_MB_U_ROW_ADDR 0x013C 616 617 /* Register CR_CURR_MB_V_ROW_ADDR */ 618 #define MVEA_CR_CURR_MB_V_ROW_ADDR 0x0140 619 #define MASK_MVEA_CR_CURR_MB_V_ROW_ADDR 0xFFFFFFFF 620 #define SHIFT_MVEA_CR_CURR_MB_V_ROW_ADDR 0 621 #define REGNUM_MVEA_CR_CURR_MB_V_ROW_ADDR 0x0140 622 623 /* Register CR_CURR_MB_Y_ROW_STRIDE */ 624 #define MVEA_CR_CURR_MB_Y_ROW_STRIDE 0x0144 625 #define MASK_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0x0000FFFF 626 #define SHIFT_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0 627 #define REGNUM_MVEA_CR_CURR_MB_Y_ROW_OFFSET 0x0144 628 629 /* Register CR_CURR_MB_UV_ROW_STRIDE */ 630 #define MVEA_CR_CURR_MB_UV_ROW_STRIDE 0x0148 631 #define MASK_MVEA_CR_CURR_MB_V_ROW_OFFSET 0x0000FFFF 632 #define SHIFT_MVEA_CR_CURR_MB_V_ROW_OFFSET 0 633 #define REGNUM_MVEA_CR_CURR_MB_V_ROW_OFFSET 0x0148 634 635 #define MASK_MVEA_CR_CURR_MB_U_ROW_OFFSET 0xFFFF0000 636 #define SHIFT_MVEA_CR_CURR_MB_U_ROW_OFFSET 16 637 #define REGNUM_MVEA_CR_CURR_MB_U_ROW_OFFSET 0x0148 638 639 /* Register CR_REF_Y_ROW_ADDR */ 640 #define MVEA_CR_REF_Y_ROW_ADDR 0x014C 641 #define MASK_MVEA_CR_REF_Y_ROW_ADDR 0xFFFFFFFF 642 #define SHIFT_MVEA_CR_REF_Y_ROW_ADDR 0 643 #define REGNUM_MVEA_CR_REF_Y_ROW_ADDR 0x014C 644 645 /* Register CR_REF_UV_ROW_ADDR */ 646 #define MVEA_CR_REF_UV_ROW_ADDR 0x0150 647 #define MASK_MVEA_CR_REF_UV_ROW_ADDR 0xFFFFFFFF 648 #define SHIFT_MVEA_CR_REF_UV_ROW_ADDR 0 649 #define REGNUM_MVEA_CR_REF_UV_ROW_ADDR 0x0150 650 651 /* Register CR_REF_ROW_STRIDE */ 652 #define MVEA_CR_REF_ROW_STRIDE 0x0154 653 #define MASK_MVEA_CR_REF_UV_ROW_OFFSET 0x0000FFFF 654 #define SHIFT_MVEA_CR_REF_UV_ROW_OFFSET 0 655 #define REGNUM_MVEA_CR_REF_UV_ROW_OFFSET 0x0154 656 657 #define MASK_MVEA_CR_REF_Y_ROW_OFFSET 0xFFFF0000 658 #define SHIFT_MVEA_CR_REF_Y_ROW_OFFSET 16 659 #define REGNUM_MVEA_CR_REF_Y_ROW_OFFSET 0x0154 660 661 /* Register CR_ABOVE_PIX_Y_ROW_IN_ADDR */ 662 #define MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0x0158 663 #define MASK_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0xFFFFFFFF 664 #define SHIFT_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0 665 #define REGNUM_MVEA_CR_ABOVE_PIX_Y_ROW_IN_ADDR 0x0158 666 667 /* Register CR_ABOVE_PIX_UV_ROW_IN_ADDR */ 668 #define MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0x015C 669 #define MASK_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0xFFFFFFFF 670 #define SHIFT_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0 671 #define REGNUM_MVEA_CR_ABOVE_PIX_UV_ROW_IN_ADDR 0x015C 672 673 /* Register CR_RECON_Y_ROW_ADDR */ 674 #define MVEA_CR_RECON_Y_ROW_ADDR 0x0160 675 #define MASK_MVEA_CR_RECON_Y_ROW_ADDR 0xFFFFFFFF 676 #define SHIFT_MVEA_CR_RECON_Y_ROW_ADDR 0 677 #define REGNUM_MVEA_CR_RECON_Y_ROW_ADDR 0x0160 678 679 /* Register CR_RECON_UV_ROW_ADDR */ 680 #define MVEA_CR_RECON_UV_ROW_ADDR 0x0164 681 #define MASK_MVEA_CR_RECON_UV_ROW_ADDR 0xFFFFFFFF 682 #define SHIFT_MVEA_CR_RECON_UV_ROW_ADDR 0 683 #define REGNUM_MVEA_CR_RECON_UV_ROW_ADDR 0x0164 684 685 /* Register CR_ABOVE_PARAM_ADDR */ 686 #define MVEA_CR_ABOVE_PARAM_ADDR 0x0168 687 #define MASK_MVEA_CR_ABOVE_PARAM_ADDR 0xFFFFFFFF 688 #define SHIFT_MVEA_CR_ABOVE_PARAM_ADDR 0 689 #define REGNUM_MVEA_CR_ABOVE_PARAM_ADDR 0x0168 690 691 /* Register CR_CURR_PARAM_ADDR */ 692 #define MVEA_CR_CURR_PARAM_ADDR 0x016C 693 #define MASK_MVEA_CR_CURR_PARAM_ADDR 0xFFFFFFFF 694 #define SHIFT_MVEA_CR_CURR_PARAM_ADDR 0 695 #define REGNUM_MVEA_CR_CURR_PARAM_ADDR 0x016C 696 697 /* Register CR_BELOW_PARAM_IN_ADDR */ 698 #define MVEA_CR_BELOW_PARAM_IN_ADDR 0x0170 699 #define MASK_MVEA_CR_BELOW_PARAM_IN_ADDR 0xFFFFFFFF 700 #define SHIFT_MVEA_CR_BELOW_PARAM_IN_ADDR 0 701 #define REGNUM_MVEA_CR_BELOW_PARAM_IN_ADDR 0x0170 702 703 /* Register CR_LRB_LOAD */ 704 #define MVEA_CR_LRB_LOAD 0x0174 705 #define MASK_MVEA_CR_LRB_LOAD_MB_NO_0 0x0000000F 706 #define SHIFT_MVEA_CR_LRB_LOAD_MB_NO_0 0 707 #define REGNUM_MVEA_CR_LRB_LOAD_MB_NO_0 0x0174 708 709 #define MASK_MVEA_CR_LRB_LOAD_MB_NO_1 0x000000F0 710 #define SHIFT_MVEA_CR_LRB_LOAD_MB_NO_1 4 711 #define REGNUM_MVEA_CR_LRB_LOAD_MB_NO_1 0x0174 712 713 #define MASK_MVEA_CR_LRB_LOAD_Y_OFFSET 0x00000F00 714 #define SHIFT_MVEA_CR_LRB_LOAD_Y_OFFSET 8 715 #define REGNUM_MVEA_CR_LRB_LOAD_Y_OFFSET 0x0174 716 717 /* Register CR_BELOW_PARAM_OUT_ADDR */ 718 #define MVEA_CR_BELOW_PARAM_OUT_ADDR 0x0178 719 #define MASK_MVEA_CR_BELOW_PARAM_OUT_ADDR 0xFFFFFFFF 720 #define SHIFT_MVEA_CR_BELOW_PARAM_OUT_ADDR 0 721 #define REGNUM_MVEA_CR_BELOW_PARAM_OUT_ADDR 0x0178 722 723 /* Register CR_BUFFER_SIDEBAND */ 724 #define MVEA_CR_BUFFER_SIDEBAND 0x017C 725 #define MASK_MVEA_CR_CURR_MB_SBAND 0x00000003 726 #define SHIFT_MVEA_CR_CURR_MB_SBAND 0 727 #define REGNUM_MVEA_CR_CURR_MB_SBAND 0x017C 728 729 #define MASK_MVEA_CR_ABOVE_PIX_IN_SBAND 0x0000000C 730 #define SHIFT_MVEA_CR_ABOVE_PIX_IN_SBAND 2 731 #define REGNUM_MVEA_CR_ABOVE_PIX_IN_SBAND 0x017C 732 733 #define MASK_MVEA_CR_CURR_PARAM_SBAND 0x00000030 734 #define SHIFT_MVEA_CR_CURR_PARAM_SBAND 4 735 #define REGNUM_MVEA_CR_CURR_PARAM_SBAND 0x017C 736 737 #define MASK_MVEA_CR_BELOW_PARAM_IN_SBAND 0x000000C0 738 #define SHIFT_MVEA_CR_BELOW_PARAM_IN_SBAND 6 739 #define REGNUM_MVEA_CR_BELOW_PARAM_IN_SBAND 0x017C 740 741 #define MASK_MVEA_CR_ABOVE_PARAM_IN_SBAND 0x00000300 742 #define SHIFT_MVEA_CR_ABOVE_PARAM_IN_SBAND 8 743 #define REGNUM_MVEA_CR_ABOVE_PARAM_IN_SBAND 0x017C 744 745 #define MASK_MVEA_CR_REF_SBAND 0x00000C00 746 #define SHIFT_MVEA_CR_REF_SBAND 10 747 #define REGNUM_MVEA_CR_REF_SBAND 0x017C 748 749 #define MASK_MVEA_CR_RECON_SBAND 0x00003000 750 #define SHIFT_MVEA_CR_RECON_SBAND 12 751 #define REGNUM_MVEA_CR_RECON_SBAND 0x017C 752 753 #define MASK_MVEA_CR_ABOVE_PIX_OUT_SBAND 0x0000C000 754 #define SHIFT_MVEA_CR_ABOVE_PIX_OUT_SBAND 14 755 #define REGNUM_MVEA_CR_ABOVE_PIX_OUT_SBAND 0x017C 756 757 #define MASK_MVEA_CR_BELOW_PARAM_OUT_SBAND 0x00030000 758 #define SHIFT_MVEA_CR_BELOW_PARAM_OUT_SBAND 16 759 #define REGNUM_MVEA_CR_BELOW_PARAM_OUT_SBAND 0x017C 760 761 #define MASK_MVEA_CR_ABOVE_PARAM_OUT_SBAND 0x000C0000 762 #define SHIFT_MVEA_CR_ABOVE_PARAM_OUT_SBAND 18 763 #define REGNUM_MVEA_CR_ABOVE_PARAM_OUT_SBAND 0x017C 764 765 /* Register CR_CMPRS_ACKNOWLEDGE */ 766 #define MVEA_CR_CMPRS_ACKNOWLEDGE 0x0180 767 #define MASK_MVEA_CR_CMPRS_ACK 0x00000001 768 #define SHIFT_MVEA_CR_CMPRS_ACK 0 769 #define REGNUM_MVEA_CR_CMPRS_ACK 0x0180 770 771 /* Register CR_CMPRS_SBLK_THRESHOLD */ 772 #define MVEA_CR_CMPRS_SBLK_THRESHOLD 0x0184 773 #define MASK_MVEA_CR_CMPRS_SBLK_THRSHLD 0x000001FF 774 #define SHIFT_MVEA_CR_CMPRS_SBLK_THRSHLD 0 775 #define REGNUM_MVEA_CR_CMPRS_SBLK_THRSHLD 0x0184 776 777 /* Register CR_CMPRS_COEFF_COST_H */ 778 #define MVEA_CR_CMPRS_COEFF_COST_H 0x0188 779 #define MASK_MVEA_CR_CMPRS_COEFF_COST8 0x0000000F 780 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST8 0 781 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST8 0x0188 782 783 #define MASK_MVEA_CR_CMPRS_COEFF_COST9 0x000000F0 784 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST9 4 785 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST9 0x0188 786 787 #define MASK_MVEA_CR_CMPRS_COEFF_COST10 0x00000F00 788 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST10 8 789 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST10 0x0188 790 791 #define MASK_MVEA_CR_CMPRS_COEFF_COST11 0x0000F000 792 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST11 12 793 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST11 0x0188 794 795 #define MASK_MVEA_CR_CMPRS_COEFF_COST12 0x000F0000 796 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST12 16 797 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST12 0x0188 798 799 #define MASK_MVEA_CR_CMPRS_COEFF_COST13 0x00F00000 800 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST13 20 801 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST13 0x0188 802 803 #define MASK_MVEA_CR_CMPRS_COEFF_COST14 0x0F000000 804 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST14 24 805 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST14 0x0188 806 807 #define MASK_MVEA_CR_CMPRS_COEFF_COST15 0xF0000000 808 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST15 28 809 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST15 0x0188 810 811 /* Register CR_CMPRS_COEFF_COST_L */ 812 #define MVEA_CR_CMPRS_COEFF_COST_L 0x018C 813 #define MASK_MVEA_CR_CMPRS_COEFF_COST0 0x0000000F 814 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST0 0 815 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST0 0x018C 816 817 #define MASK_MVEA_CR_CMPRS_COEFF_COST1 0x000000F0 818 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST1 4 819 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST1 0x018C 820 821 #define MASK_MVEA_CR_CMPRS_COEFF_COST2 0x00000F00 822 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST2 8 823 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST2 0x018C 824 825 #define MASK_MVEA_CR_CMPRS_COEFF_COST3 0x0000F000 826 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST3 12 827 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST3 0x018C 828 829 #define MASK_MVEA_CR_CMPRS_COEFF_COST4 0x000F0000 830 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST4 16 831 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST4 0x018C 832 833 #define MASK_MVEA_CR_CMPRS_COEFF_COST5 0x00F00000 834 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST5 20 835 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST5 0x018C 836 837 #define MASK_MVEA_CR_CMPRS_COEFF_COST6 0x0F000000 838 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST6 24 839 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST6 0x018C 840 841 #define MASK_MVEA_CR_CMPRS_COEFF_COST7 0xF0000000 842 #define SHIFT_MVEA_CR_CMPRS_COEFF_COST7 28 843 #define REGNUM_MVEA_CR_CMPRS_COEFF_COST7 0x018C 844 845 /* Register CR_CMPRS_COEFF_THRESHOLD */ 846 #define MVEA_CR_CMPRS_COEFF_THRESHOLD 0x0190 847 #define MASK_MVEA_CR_CMPRS_COEFF_THRSHLD 0x0000FFFF 848 #define SHIFT_MVEA_CR_CMPRS_COEFF_THRSHLD 0 849 #define REGNUM_MVEA_CR_CMPRS_COEFF_THRSHLD 0x0190 850 851 /* Register CR_CMPRS_SBLK_RIGHT */ 852 #define MVEA_CR_CMPRS_SBLK_RIGHT 0x0194 853 #define MASK_MVEA_CR_CMPRS_SBLK_RIGHT 0xFFFFFFFF 854 #define SHIFT_MVEA_CR_CMPRS_SBLK_RIGHT 0 855 #define REGNUM_MVEA_CR_CMPRS_SBLK_RIGHT 0x0194 856 857 /* Register CR_CMPRS_SBLK_BOTTOM */ 858 #define MVEA_CR_CMPRS_SBLK_BOTTOM 0x0198 859 #define MASK_MVEA_CR_CMPRS_SBLK_BOTTOM 0x00FFFFFF 860 #define SHIFT_MVEA_CR_CMPRS_SBLK_BOTTOM 0 861 #define REGNUM_MVEA_CR_CMPRS_SBLK_BOTTOM 0x0198 862 863 /* Register CR_CMPRS_TRANS_CRC */ 864 #define MVEA_CR_CMPRS_TRANS_CRC 0x019C 865 #define MASK_MVEA_CR_CMPRS_IT_CRC 0x0000FFFF 866 #define SHIFT_MVEA_CR_CMPRS_IT_CRC 0 867 #define REGNUM_MVEA_CR_CMPRS_IT_CRC 0x019C 868 869 #define MASK_MVEA_CR_CMPRS_FT_CRC 0xFFFF0000 870 #define SHIFT_MVEA_CR_CMPRS_FT_CRC 16 871 #define REGNUM_MVEA_CR_CMPRS_FT_CRC 0x019C 872 873 /* Register CR_CMPRS_QUANT_CRC */ 874 #define MVEA_CR_CMPRS_QUANT_CRC 0x01A0 875 #define MASK_MVEA_CR_CMPRS_IQT_CRC 0x0000FFFF 876 #define SHIFT_MVEA_CR_CMPRS_IQT_CRC 0 877 #define REGNUM_MVEA_CR_CMPRS_IQT_CRC 0x01A0 878 879 #define MASK_MVEA_CR_CMPRS_QT_CRC 0xFFFF0000 880 #define SHIFT_MVEA_CR_CMPRS_QT_CRC 16 881 #define REGNUM_MVEA_CR_CMPRS_QT_CRC 0x01A0 882 883 /* Register CR_CMPRS_DIAGNOSTIC1 */ 884 #define MVEA_CR_CMPRS_DIAGNOSTIC1 0x01A4 885 #define MASK_MVEA_CR_CMPRS_DIAG1 0xFFFFFFFF 886 #define SHIFT_MVEA_CR_CMPRS_DIAG1 0 887 #define REGNUM_MVEA_CR_CMPRS_DIAG1 0x01A4 888 889 /* Register CR_CMPRS_RLE_CONTROL */ 890 #define MVEA_CR_CMPRS_RLE_CONTROL 0x01A8 891 #define MASK_MVEA_CR_CMPRS_RLE_ENABLE 0x80000000 892 #define SHIFT_MVEA_CR_CMPRS_RLE_ENABLE 31 893 #define REGNUM_MVEA_CR_CMPRS_RLE_ENABLE 0x01A8 894 895 /* Register CR_CMPRS_RLE_STATUS */ 896 #define MVEA_CR_CMPRS_RLE_STATUS 0x01AC 897 #define MASK_MVEA_CR_CMPRS_CODED_COUNT 0x000007FF 898 #define SHIFT_MVEA_CR_CMPRS_CODED_COUNT 0 899 #define REGNUM_MVEA_CR_CMPRS_CODED_COUNT 0x01AC 900 901 /* Register CR_CMPRS_MAX_CYCLE_COUNT */ 902 #define MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x01B0 903 #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x0000FFFF 904 #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0 905 #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_COUNT 0x01B0 906 907 /* Register CR_CMPRS_MAX_CYCLE_MB */ 908 #define MVEA_CR_CMPRS_MAX_CYCLE_MB 0x01B4 909 #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0x003FFFFF 910 #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0 911 #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_MB_NUM 0x01B4 912 913 #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 0x30000000 914 #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 28 915 #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_MB_TYPE 0x01B4 916 917 /* Register CR_CMPRS_MAX_CYCLE_RESET */ 918 #define MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x01B8 919 #define MASK_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x00000001 920 #define SHIFT_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0 921 #define REGNUM_MVEA_CR_CMPRS_MAX_CYCLE_RESET 0x01B8 922 923 #define MASK_MVEA_CR_CMPRS_DISABLE_COUNTERS 0x00000002 924 #define SHIFT_MVEA_CR_CMPRS_DISABLE_COUNTERS 1 925 #define REGNUM_MVEA_CR_CMPRS_DISABLE_COUNTERS 0x01B8 926 927 /* Register CR_CMPRS_VLC_CRC */ 928 #define MVEA_CR_CMPRS_VLC_CRC 0x01BC 929 #define MASK_MVEA_CR_CMPRS_VLC_CRC 0x0000FFFF 930 #define SHIFT_MVEA_CR_CMPRS_VLC_CRC 0 931 #define REGNUM_MVEA_CR_CMPRS_VLC_CRC 0x01BC 932 933 /* Register CR_ABOVE_PIX_Y_ROW_OUT_ADDR */ 934 #define MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0x01C0 935 #define MASK_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0xFFFFFFFF 936 #define SHIFT_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0 937 #define REGNUM_MVEA_CR_ABOVE_PIX_Y_ROW_OUT_ADDR 0x01C0 938 939 /* Register CR_ABOVE_PIX_UV_ROW_OUT_ADDR */ 940 #define MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0x01C4 941 #define MASK_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0xFFFFFFFF 942 #define SHIFT_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0 943 #define REGNUM_MVEA_CR_ABOVE_PIX_UV_ROW_OUT_ADDR 0x01C4 944 945 /* Register CR_IPE_LAMBDA_TABLE */ 946 #define MVEA_CR_IPE_LAMBDA_TABLE 0x01F0 947 #define MASK_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0x000000FF 948 #define SHIFT_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0 949 #define REGNUM_MVEA_CR_IPE_QPC_OR_DC_SCALE_LUMA_TABLE 0x01F0 950 951 #define MASK_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 0x0000FF00 952 #define SHIFT_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 8 953 #define REGNUM_MVEA_CR_IPE_ALPHA_OR_DC_SCALE_CHR_TABLE 0x01F0 954 955 #define MASK_MVEA_CR_IPE_LAMBDA_TABLE 0x007F0000 956 #define SHIFT_MVEA_CR_IPE_LAMBDA_TABLE 16 957 #define REGNUM_MVEA_CR_IPE_LAMBDA_TABLE 0x01F0 958 959 /* Register CR_IPE_MV_BIAS_TABLE */ 960 #define MVEA_CR_IPE_MV_BIAS_TABLE 0x01F4 961 #define MASK_MVEA_CR_IPE_MV_BIAS_TABLE 0x00007FFF 962 #define SHIFT_MVEA_CR_IPE_MV_BIAS_TABLE 0 963 #define REGNUM_MVEA_CR_IPE_MV_BIAS_TABLE 0x01F4 964 965 /* Register CR_IPE_QP */ 966 #define MVEA_CR_IPE_QP 0x01FC 967 #define MASK_MVEA_CR_IPE_QPY 0x000000FF 968 #define SHIFT_MVEA_CR_IPE_QPY 0 969 #define REGNUM_MVEA_CR_IPE_QPY 0x01FC 970 971 /* Register CR_IPE_CONTROL */ 972 #define MVEA_CR_IPE_CONTROL 0x0200 973 #define MASK_MVEA_CR_IPE_BLOCKSIZE 0x00000003 974 #define SHIFT_MVEA_CR_IPE_BLOCKSIZE 0 975 #define REGNUM_MVEA_CR_IPE_BLOCKSIZE 0x0200 976 977 #define MASK_MVEA_CR_IPE_Y_CANDIDATE_NUM 0x0000003C 978 #define SHIFT_MVEA_CR_IPE_Y_CANDIDATE_NUM 2 979 #define REGNUM_MVEA_CR_IPE_Y_CANDIDATE_NUM 0x0200 980 981 #define MASK_MVEA_CR_IPE_Y_FINE_SEARCH 0x00000040 982 #define SHIFT_MVEA_CR_IPE_Y_FINE_SEARCH 6 983 #define REGNUM_MVEA_CR_IPE_Y_FINE_SEARCH 0x0200 984 985 #define MASK_MVEA_CR_IPE_GRID_SEARCH_SIZE 0x00000380 986 #define SHIFT_MVEA_CR_IPE_GRID_SEARCH_SIZE 7 987 #define REGNUM_MVEA_CR_IPE_GRID_SEARCH_SIZE 0x0200 988 989 #define MASK_MVEA_CR_IPE_GRID_FINE_SEARCH 0x00000C00 990 #define SHIFT_MVEA_CR_IPE_GRID_FINE_SEARCH 10 991 #define REGNUM_MVEA_CR_IPE_GRID_FINE_SEARCH 0x0200 992 993 #define MASK_MVEA_CR_IPE_ENCODING_FORMAT 0x00003000 994 #define SHIFT_MVEA_CR_IPE_ENCODING_FORMAT 12 995 #define REGNUM_MVEA_CR_IPE_ENCODING_FORMAT 0x0200 996 997 #define MASK_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 0x00004000 998 #define SHIFT_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 14 999 #define REGNUM_MVEA_CR_IPE_MV_NUMBER_RESTRICTION 0x0200 1000 1001 /* Register CR_IPE_SEARCH_STATUS */ 1002 #define MVEA_CR_IPE_SEARCH_STATUS 0x0204 1003 #define MASK_MVEA_CR_IPE_SEARCH_STATUS 0x00000007 1004 #define SHIFT_MVEA_CR_IPE_SEARCH_STATUS 0 1005 #define REGNUM_MVEA_CR_IPE_SEARCH_STATUS 0x0204 1006 1007 /* Register CR_IPE_INT_MVCOST */ 1008 #define MVEA_CR_IPE_INT_MVCOST 0x0208 1009 #define MASK_MVEA_CR_IPE_INT_MVCOST 0x0000FFFF 1010 #define SHIFT_MVEA_CR_IPE_INT_MVCOST 0 1011 #define REGNUM_MVEA_CR_IPE_INT_MVCOST 0x0208 1012 1013 /* Register CR_IPE_MB_SAD */ 1014 #define MVEA_CR_IPE_MB_SAD 0x020C 1015 #define MASK_MVEA_CR_IPE_MB_SAD 0x0000FFFF 1016 #define SHIFT_MVEA_CR_IPE_MB_SAD 0 1017 #define REGNUM_MVEA_CR_IPE_MB_SAD 0x020C 1018 1019 /* Register CR_IPE_DIAG1 */ 1020 #define MVEA_CR_IPE_DIAG1 0x0210 1021 #define MASK_MVEA_CR_IPE_DIAG1 0xFFFFFFFF 1022 #define SHIFT_MVEA_CR_IPE_DIAG1 0 1023 #define REGNUM_MVEA_CR_IPE_DIAG1 0x0210 1024 1025 /* Register CR_IPE_QP_SLICE */ 1026 #define MVEA_CR_IPE_QP_SLICE 0x0214 1027 #define MASK_MVEA_CR_IPE_QPY_SLICE 0x000000FF 1028 #define SHIFT_MVEA_CR_IPE_QPY_SLICE 0 1029 #define REGNUM_MVEA_CR_IPE_QPY_SLICE 0x0214 1030 1031 #define MASK_MVEA_CR_IPE_QPC_SLICE 0x0000FF00 1032 #define SHIFT_MVEA_CR_IPE_QPC_SLICE 8 1033 #define REGNUM_MVEA_CR_IPE_QPC_SLICE 0x0214 1034 1035 /* Register CR_IPE_JITTER_FACTOR */ 1036 #define MVEA_CR_IPE_JITTER_FACTOR 0x0218 1037 #define MASK_MVEA_CR_IPE_JITTER_FACTOR 0x00000003 1038 #define SHIFT_MVEA_CR_IPE_JITTER_FACTOR 0 1039 #define REGNUM_MVEA_CR_IPE_JITTER_FACTOR 0x0218 1040 1041 /* Register CR_IPE_CTRL_CRC */ 1042 #define MVEA_CR_IPE_CTRL_CRC 0x0264 1043 #define MASK_MVEA_CR_IPE_CTRL_CRC 0xFFFFFFFF 1044 #define SHIFT_MVEA_CR_IPE_CTRL_CRC 0 1045 #define REGNUM_MVEA_CR_IPE_CTRL_CRC 0x0264 1046 1047 /* Register CR_IPE_WDATA_CRC */ 1048 #define MVEA_CR_IPE_WDATA_CRC 0x0268 1049 #define MASK_MVEA_CR_IPE_WDATA_CRC 0xFFFFFFFF 1050 #define SHIFT_MVEA_CR_IPE_WDATA_CRC 0 1051 #define REGNUM_MVEA_CR_IPE_WDATA_CRC 0x0268 1052 1053 /* Register CR_IPE_MB_PERFORMANCE_CLEAR */ 1054 #define MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x026C 1055 #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x00000001 1056 #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0 1057 #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_CLEAR 0x026C 1058 1059 /* Register CR_IPE_MB_PERFORMANCE_RESULT */ 1060 #define MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0270 1061 #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0000FFFF 1062 #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0 1063 #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_RESULT 0x0270 1064 1065 /* Register CR_IPE_MB_PERFORMANCE_MB_NUMBER */ 1066 #define MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x0274 1067 #define MASK_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x003FFFFF 1068 #define SHIFT_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0 1069 #define REGNUM_MVEA_CR_IPE_MB_PERFORMANCE_MB_NUMBER 0x0274 1070 1071 /* Register CR_IPE_VECTOR_CLIPPING */ 1072 #define MVEA_CR_IPE_VECTOR_CLIPPING 0x0278 1073 #define MASK_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0x000000FF 1074 #define SHIFT_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0 1075 #define REGNUM_MVEA_CR_IPE_VECTOR_CLIPPING_Y 0x0278 1076 1077 #define MASK_MVEA_CR_IPE_VECTOR_CLIPPING_X 0x0000FF00 1078 #define SHIFT_MVEA_CR_IPE_VECTOR_CLIPPING_X 8 1079 #define REGNUM_MVEA_CR_IPE_VECTOR_CLIPPING_X 0x0278 1080 1081 /* Register CR_JMCOMP_CONTROL */ 1082 #define MVEA_CR_JMCOMP_CONTROL 0x0280 1083 #define MASK_MVEA_CR_JMCOMP_MODE 0x00000003 1084 #define SHIFT_MVEA_CR_JMCOMP_MODE 0 1085 #define REGNUM_MVEA_CR_JMCOMP_MODE 0x0280 1086 1087 #define MASK_MVEA_CR_JMCOMP_AC_ENABLE 0x00008000 1088 #define SHIFT_MVEA_CR_JMCOMP_AC_ENABLE 15 1089 #define REGNUM_MVEA_CR_JMCOMP_AC_ENABLE 0x0280 1090 1091 #define MASK_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 0x00F00000 1092 #define SHIFT_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 20 1093 #define REGNUM_MVEA_CR_JMCOMP_JPEG_NUM_BLOCKS 0x0280 1094 1095 #define MASK_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 0x01000000 1096 #define SHIFT_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 24 1097 #define REGNUM_MVEA_CR_JMCOMP_DISABLE_QP_PATCH_ON_SKIP 0x0280 1098 1099 /* Register CR_JMCOMP_JPEG_BLOCK_TYPES */ 1100 #define MVEA_CR_JMCOMP_JPEG_BLOCK_TYPES 0x0284 1101 #define MASK_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) (0x00000003 << (0 + ((i) * 2))) 1102 #define SHIFT_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) (0 + ((i) * 2)) 1103 #define REGNUM_MVEA_CR_JMCOMP_JPEG_BLOCK_TYPE(i) 0x0284 1104 1105 /* Register CR_JMCOMP_JPEG_LUMA_PRED */ 1106 #define MVEA_CR_JMCOMP_JPEG_LUMA_PRED 0x0288 1107 #define MASK_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0x00000FFF 1108 #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0 1109 #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_LUMA_PRED 0x0288 1110 1111 /* Register CR_JMCOMP_JPEG_CHROMA_PREDS */ 1112 #define MVEA_CR_JMCOMP_JPEG_CHROMA_PREDS 0x028C 1113 #define MASK_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 0x0FFF0000 1114 #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 16 1115 #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_V_PRED 0x028C 1116 1117 #define MASK_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0x00000FFF 1118 #define SHIFT_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0 1119 #define REGNUM_MVEA_CR_JMCOMP_JPEG_DC_CHROMA_U_PRED 0x028C 1120 1121 /* Register CR_JMCOMP_CRC */ 1122 #define MVEA_CR_JMCOMP_CRC 0x0314 1123 #define MASK_MVEA_CR_JMCOMP_CRC_OUT 0xFFFFFFFF 1124 #define SHIFT_MVEA_CR_JMCOMP_CRC_OUT 0 1125 #define REGNUM_MVEA_CR_JMCOMP_CRC_OUT 0x0314 1126 1127 /* Register CR_JMCOMP_VLC_CRC */ 1128 #define MVEA_CR_JMCOMP_VLC_CRC 0x0318 1129 #define MASK_MVEA_CR_JMCOMP_VLC_IF_CRC 0xFFFFFFFF 1130 #define SHIFT_MVEA_CR_JMCOMP_VLC_IF_CRC 0 1131 #define REGNUM_MVEA_CR_JMCOMP_VLC_IF_CRC 0x0318 1132 1133 /* Register CR_JMCOMP_PERFORMANCE_0 */ 1134 #define MVEA_CR_JMCOMP_PERFORMANCE_0 0x031C 1135 #define MASK_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0x0000FFFF 1136 #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0 1137 #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_CYCLES 0x031C 1138 1139 #define MASK_MVEA_CR_JMCOMP_WORST_MB_TYPE 0x00030000 1140 #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_TYPE 16 1141 #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_TYPE 0x031C 1142 1143 /* Register CR_JMCOMP_PERFORMANCE_1 */ 1144 #define MVEA_CR_JMCOMP_PERFORMANCE_1 0x0320 1145 #define MASK_MVEA_CR_JMCOMP_WORST_MB_NUM 0x003FFFFF 1146 #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_NUM 0 1147 #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_NUM 0x0320 1148 1149 /* Register CR_JMCOMP_PERFORMANCE_2 */ 1150 #define MVEA_CR_JMCOMP_PERFORMANCE_2 0x0324 1151 #define MASK_MVEA_CR_JMCOMP_WORST_MB_RESET 0x00000001 1152 #define SHIFT_MVEA_CR_JMCOMP_WORST_MB_RESET 0 1153 #define REGNUM_MVEA_CR_JMCOMP_WORST_MB_RESET 0x0324 1154 1155 #define MASK_MVEA_CR_JMCOMP_DISABLE_COUNTERS 0x00000002 1156 #define SHIFT_MVEA_CR_JMCOMP_DISABLE_COUNTERS 1 1157 #define REGNUM_MVEA_CR_JMCOMP_DISABLE_COUNTERS 0x0324 1158 1159 /* Register CR_JMCOMP_QP_VALUE */ 1160 #define MVEA_CR_JMCOMP_QP_VALUE 0x0348 1161 #define MASK_MVEA_CR_JMCOMP_REAL_QP_LUMA 0x000001FF 1162 #define SHIFT_MVEA_CR_JMCOMP_REAL_QP_LUMA 0 1163 #define REGNUM_MVEA_CR_JMCOMP_REAL_QP_LUMA 0x0348 1164 1165 /* Register CR_SPE_ZERO_THRESH */ 1166 #define MVEA_CR_SPE_ZERO_THRESH 0x0370 1167 #define MASK_MVEA_CR_SPE_ZERO_THRESH 0x0000001F 1168 #define SHIFT_MVEA_CR_SPE_ZERO_THRESH 0 1169 #define REGNUM_MVEA_CR_SPE_ZERO_THRESH 0x0370 1170 1171 /* Register CR_SPE_INTRA16_BIAS_TABLE */ 1172 #define MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0374 1173 #define MASK_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0003FFFF 1174 #define SHIFT_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0 1175 #define REGNUM_MVEA_CR_SPE_INTRA16_BIAS_TABLE 0x0374 1176 1177 /* Register CR_SPE_INTER_BIAS_TABLE */ 1178 #define MVEA_CR_SPE_INTER_BIAS_TABLE 0x0378 1179 #define MASK_MVEA_CR_SPE_INTER_BIAS_TABLE 0x0003FFFF 1180 #define SHIFT_MVEA_CR_SPE_INTER_BIAS_TABLE 0 1181 #define REGNUM_MVEA_CR_SPE_INTER_BIAS_TABLE 0x0378 1182 1183 /* Register CR_SPE_PRED_VECTOR_BIAS_TABLE */ 1184 #define MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x037C 1185 #define MASK_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x00007FFF 1186 #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0 1187 #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE 0x037C 1188 1189 /* Register CR_SPE_CONTROL */ 1190 #define MVEA_CR_SPE_CONTROL 0x0380 1191 #define MASK_MVEA_CR_SPE_INTER_ENABLE 0x00000001 1192 #define SHIFT_MVEA_CR_SPE_INTER_ENABLE 0 1193 #define REGNUM_MVEA_CR_SPE_INTER_ENABLE 0x0380 1194 1195 #define MASK_MVEA_CR_SPE_INTRA_ENABLE 0x00000002 1196 #define SHIFT_MVEA_CR_SPE_INTRA_ENABLE 1 1197 #define REGNUM_MVEA_CR_SPE_INTRA_ENABLE 0x0380 1198 1199 #define MASK_MVEA_CR_SPE_MPEG4_ENABLE 0x00000004 1200 #define SHIFT_MVEA_CR_SPE_MPEG4_ENABLE 2 1201 #define REGNUM_MVEA_CR_SPE_MPEG4_ENABLE 0x0380 1202 1203 #define MASK_MVEA_CR_SPE_FORCE_SKIP 0x00000008 1204 #define SHIFT_MVEA_CR_SPE_FORCE_SKIP 3 1205 #define REGNUM_MVEA_CR_SPE_FORCE_SKIP 0x0380 1206 1207 #define MASK_MVEA_CR_SPE_H263_ENABLE 0x00000010 1208 #define SHIFT_MVEA_CR_SPE_H263_ENABLE 4 1209 #define REGNUM_MVEA_CR_SPE_H263_ENABLE 0x0380 1210 1211 /* Register CR_SPE_INTRA_COST */ 1212 #define MVEA_CR_SPE_INTRA_COST 0x0384 1213 #define MASK_MVEA_CR_SPE_INTRA_COST 0x0001FFFF 1214 #define SHIFT_MVEA_CR_SPE_INTRA_COST 0 1215 #define REGNUM_MVEA_CR_SPE_INTRA_COST 0x0384 1216 1217 /* Register CR_SPE_REQUEST */ 1218 #define MVEA_CR_SPE_REQUEST 0x038C 1219 #define MASK_MVEA_CR_SPE_REQ 0x00000001 1220 #define SHIFT_MVEA_CR_SPE_REQ 0 1221 #define REGNUM_MVEA_CR_SPE_REQ 0x038C 1222 1223 /* Register CR_SPE_INTER_SUM_MIN_SADS */ 1224 #define MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0390 1225 #define MASK_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0000FFFF 1226 #define SHIFT_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0 1227 #define REGNUM_MVEA_CR_SPE_INTER_SUM_MIN_SADS 0x0390 1228 1229 /* Register CR_SPE_DIAGNOSTIC1 */ 1230 #define MVEA_CR_SPE_DIAGNOSTIC1 0x0394 1231 #define MASK_MVEA_CR_SPE_DIAG1 0xFFFFFFFF 1232 #define SHIFT_MVEA_CR_SPE_DIAG1 0 1233 #define REGNUM_MVEA_CR_SPE_DIAG1 0x0394 1234 1235 /* Register CR_SPE_INTER_SAD_SIGNATURE */ 1236 #define MVEA_CR_SPE_INTER_SAD_SIGNATURE 0x0398 1237 #define MASK_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0xFFFFFFFF 1238 #define SHIFT_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0 1239 #define REGNUM_MVEA_CR_SPE_INTER_SAD_SIGNATURE 0x0398 1240 1241 /* Register CR_SPE_INTRA_SAD_SIGNATURE */ 1242 #define MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0x039C 1243 #define MASK_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0xFFFFFFFF 1244 #define SHIFT_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0 1245 #define REGNUM_MVEA_CR_SPE_INTRA_SAD_SIGNATURE 0x039C 1246 1247 /* Register CR_SPE_MVD_CLIP_RANGE */ 1248 #define MVEA_CR_SPE_MVD_CLIP_RANGE 0x03A0 1249 #define MASK_MVEA_CR_SPE_MVD_X_CLIP 0x0000FFFF 1250 #define SHIFT_MVEA_CR_SPE_MVD_X_CLIP 0 1251 #define REGNUM_MVEA_CR_SPE_MVD_X_CLIP 0x03A0 1252 1253 #define MASK_MVEA_CR_SPE_MVD_Y_CLIP 0xFFFF0000 1254 #define SHIFT_MVEA_CR_SPE_MVD_Y_CLIP 16 1255 #define REGNUM_MVEA_CR_SPE_MVD_Y_CLIP 0x03A0 1256 1257 /* Register CR_SPE_INT_MVCOST */ 1258 #define MVEA_CR_SPE_INT_MVCOST 0x03A4 1259 #define MASK_MVEA_CR_SPE_MVCOST 0x0000FFFF 1260 #define SHIFT_MVEA_CR_SPE_MVCOST 0 1261 #define REGNUM_MVEA_CR_SPE_MVCOST 0x03A4 1262 1263 /* Register CR_IMG_MVEA_RSVD0 */ 1264 #define MVEA_CR_IMG_MVEA_RSVD0 0x03B0 1265 #define MASK_MVEA_CR_IMG_MVEA_RESERVED0 0xFFFFFFFF 1266 #define SHIFT_MVEA_CR_IMG_MVEA_RESERVED0 0 1267 #define REGNUM_MVEA_CR_IMG_MVEA_RESERVED0 0x03B0 1268 1269 /* Register CR_MVEA_CRC_RESET */ 1270 #define MVEA_CR_MVEA_CRC_RESET 0x03B4 1271 #define MASK_MVEA_CR_IPE_CRC_RST 0x00000001 1272 #define SHIFT_MVEA_CR_IPE_CRC_RST 0 1273 #define REGNUM_MVEA_CR_IPE_CRC_RST 0x03B4 1274 1275 #define MASK_MVEA_CR_SPE_CRC_RST 0x00000002 1276 #define SHIFT_MVEA_CR_SPE_CRC_RST 1 1277 #define REGNUM_MVEA_CR_SPE_CRC_RST 0x03B4 1278 1279 #define MASK_MVEA_CR_CMC_CRC_RST 0x00000004 1280 #define SHIFT_MVEA_CR_CMC_CRC_RST 2 1281 #define REGNUM_MVEA_CR_CMC_CRC_RST 0x03B4 1282 1283 #define MASK_MVEA_CR_JMCOMP_CRC_RST 0x00000008 1284 #define SHIFT_MVEA_CR_JMCOMP_CRC_RST 3 1285 #define REGNUM_MVEA_CR_JMCOMP_CRC_RST 0x03B4 1286 1287 #define MASK_MVEA_CR_CMPRS_CRC_RST 0x00000010 1288 #define SHIFT_MVEA_CR_CMPRS_CRC_RST 4 1289 #define REGNUM_MVEA_CR_CMPRS_CRC_RST 0x03B4 1290 1291 #define MASK_MVEA_CR_DB_CRC_RST 0x00000020 1292 #define SHIFT_MVEA_CR_DB_CRC_RST 5 1293 #define REGNUM_MVEA_CR_DB_CRC_RST 0x03B4 1294 1295 #define MASK_MVEA_CR_VLC_CRC_RST 0x00000040 1296 #define SHIFT_MVEA_CR_VLC_CRC_RST 6 1297 #define REGNUM_MVEA_CR_VLC_CRC_RST 0x03B4 1298 1299 /* Register CR_SPE_MB_COUNT */ 1300 #define MVEA_CR_SPE_MB_COUNT 0x03BC 1301 #define MASK_MVEA_CR_SPE_INTER_MB_COUNT 0x03FF0000 1302 #define SHIFT_MVEA_CR_SPE_INTER_MB_COUNT 16 1303 #define REGNUM_MVEA_CR_SPE_INTER_MB_COUNT 0x03BC 1304 1305 #define MASK_MVEA_CR_SPE_INTRA_MB_COUNT 0x000003FF 1306 #define SHIFT_MVEA_CR_SPE_INTRA_MB_COUNT 0 1307 #define REGNUM_MVEA_CR_SPE_INTRA_MB_COUNT 0x03BC 1308 1309 /* Register CR_SPE_PRED_VECTOR */ 1310 #define MVEA_CR_SPE_PRED_VECTOR 0x03D4 1311 #define MASK_MVEA_CR_SPE_PRED_VECTOR_Y 0x7FFF0000 1312 #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_Y 16 1313 #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_Y 0x03D4 1314 1315 #define MASK_MVEA_CR_SPE_PRED_VECTOR_X 0x00007FFF 1316 #define SHIFT_MVEA_CR_SPE_PRED_VECTOR_X 0 1317 #define REGNUM_MVEA_CR_SPE_PRED_VECTOR_X 0x03D4 1318 1319 /* Register CR_SPE_MAX_CYCLE_COUNT */ 1320 #define MVEA_CR_SPE_MAX_CYCLE_COUNT 0x03D8 1321 #define MASK_MVEA_CR_SPE_MAX_CYCLE_COUNT 0x0000FFFF 1322 #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_COUNT 0 1323 #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_COUNT 0x03D8 1324 1325 /* Register CR_SPE_MAX_CYCLE_MB */ 1326 #define MVEA_CR_SPE_MAX_CYCLE_MB 0x03DC 1327 #define MASK_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 0xC0000000 1328 #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 30 1329 #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_MB_TYPE 0x03DC 1330 1331 #define MASK_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0x003FFFFF 1332 #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0 1333 #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_MB_NUM 0x03DC 1334 1335 /* Register CR_SPE_INTRA_SUM_MIN_SADS */ 1336 #define MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x03E0 1337 #define MASK_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x0000FFFF 1338 #define SHIFT_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0 1339 #define REGNUM_MVEA_CR_SPE_INTRA_SUM_MIN_SADS 0x03E0 1340 1341 /* Register CR_SPE_MAX_CYCLE_RESET */ 1342 #define MVEA_CR_SPE_MAX_CYCLE_RESET 0x03E4 1343 #define MASK_MVEA_CR_SPE_MAX_CYCLE_RESET 0x00000001 1344 #define SHIFT_MVEA_CR_SPE_MAX_CYCLE_RESET 0 1345 #define REGNUM_MVEA_CR_SPE_MAX_CYCLE_RESET 0x03E4 1346 1347 /* Register CR_SEQUENCER_SYNC */ 1348 #define MVEA_CR_SEQUENCER_SYNC 0x03E8 1349 #define MASK_MVEA_CR_SYNC_ENABLE 0x0000FFFF 1350 #define SHIFT_MVEA_CR_SYNC_ENABLE 0 1351 #define REGNUM_MVEA_CR_SYNC_ENABLE 0x03E8 1352 1353 /* Register CR_IPE_SKIPPED_MV */ 1354 #define MVEA_CR_IPE_SKIPPED_MV 0x03EC 1355 #define MASK_MVEA_CR_IPE_SKIPPED_MV_X 0x0000FF00 1356 #define SHIFT_MVEA_CR_IPE_SKIPPED_MV_X 8 1357 #define REGNUM_MVEA_CR_IPE_SKIPPED_MV_X 0x03EC 1358 1359 #define MASK_MVEA_CR_IPE_SKIPPED_MV_Y 0x000000FF 1360 #define SHIFT_MVEA_CR_IPE_SKIPPED_MV_Y 0 1361 #define REGNUM_MVEA_CR_IPE_SKIPPED_MV_Y 0x03EC 1362 1363 1364 /* Table CR_JMCOMP_CHROMA_QUANTISER_TABLE */ 1365 1366 /* Register CR_JMCOMP_CHROMA_QUANTISER */ 1367 #define MVEA_CR_JMCOMP_CHROMA_QUANTISER(X) (0x02D0 + (4 * (X))) 1368 #define MASK_MVEA_CR_JMCOMP_CHROMA_QUANT(i) (0x000000FF << (0 + ((i) * 8))) 1369 #define SHIFT_MVEA_CR_JMCOMP_CHROMA_QUANT(i) (0 + ((i) * 8)) 1370 #define REGNUM_MVEA_CR_JMCOMP_CHROMA_QUANT(X,i) (0x02D0 + (4 * (X))) 1371 1372 /* Number of entries in table CR_JMCOMP_CHROMA_QUANTISER_TABLE */ 1373 1374 #define MVEA_CR_JMCOMP_CHROMA_QUANTISER_TABLE_SIZE_UINT32 16 1375 #define MVEA_CR_JMCOMP_CHROMA_QUANTISER_TABLE_NUM_ENTRIES 16 1376 1377 1378 /* Table CR_JMCOMP_LUMA_QUANTISER_TABLE */ 1379 1380 /* Register CR_JMCOMP_LUMA_QUANTISER */ 1381 #define MVEA_CR_JMCOMP_LUMA_QUANTISER(X) (0x0290 + (4 * (X))) 1382 #define MASK_MVEA_CR_JMCOMP_LUMA_QUANT(i) (0x000000FF << (0 + ((i) * 8))) 1383 #define SHIFT_MVEA_CR_JMCOMP_LUMA_QUANT(i) (0 + ((i) * 8)) 1384 #define REGNUM_MVEA_CR_JMCOMP_LUMA_QUANT(X,i) (0x0290 + (4 * (X))) 1385 1386 /* Number of entries in table CR_JMCOMP_LUMA_QUANTISER_TABLE */ 1387 1388 #define MVEA_CR_JMCOMP_LUMA_QUANTISER_TABLE_SIZE_UINT32 16 1389 #define MVEA_CR_JMCOMP_LUMA_QUANTISER_TABLE_NUM_ENTRIES 16 1390 1391 1392 /* Table CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE */ 1393 1394 /* Register CR_CMC_ESB_LOGICAL_REGION_SETUP */ 1395 #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP(X) (0x0080 + (4 * (X))) 1396 #define MASK_MVEA_CR_CMC_ESB_REGION_VALID 0x80000000 1397 #define SHIFT_MVEA_CR_CMC_ESB_REGION_VALID 31 1398 #define REGNUM_MVEA_CR_CMC_ESB_REGION_VALID 0x0080 1399 1400 #define MASK_MVEA_CR_CMC_ESB_REGION_TYPE 0x60000000 1401 #define SHIFT_MVEA_CR_CMC_ESB_REGION_TYPE 29 1402 #define REGNUM_MVEA_CR_CMC_ESB_REGION_TYPE 0x0080 1403 1404 #define MASK_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 0x00F00000 1405 #define SHIFT_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 20 1406 #define REGNUM_MVEA_CR_CMC_ESB_REGION_LOGICAL_WIDTH 0x0080 1407 1408 #define MASK_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 0x000F0000 1409 #define SHIFT_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 16 1410 #define REGNUM_MVEA_CR_CMC_ESB_REGION_LOGICAL_OFFSET_X 0x0080 1411 1412 #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 0x0000F000 1413 #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 12 1414 #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_HEIGHT 0x0080 1415 1416 #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 0x00000F00 1417 #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 8 1418 #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_WIDTH 0x0080 1419 1420 #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 0x000000F0 1421 #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 4 1422 #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_Y 0x0080 1423 1424 #define MASK_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0x0000000F 1425 #define SHIFT_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0 1426 #define REGNUM_MVEA_CR_CMC_ESB_REGION_PHYS_ORIGIN_X 0x0080 1427 1428 /* Number of entries in table CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE */ 1429 1430 #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE_SIZE_UINT32 32 1431 #define MVEA_CR_CMC_ESB_LOGICAL_REGION_SETUP_TABLE_NUM_ENTRIES 32 1432 1433 /* 1434 Byte range covering the group MVEA file 1435 */ 1436 1437 #define MVEA_MVEA_REGISTERS_START 0x00000000 1438 #define MVEA_MVEA_REGISTERS_END 0x000003EF 1439 1440 /* 1441 Byte range covering the whole register file 1442 */ 1443 1444 #define MVEA_REGISTERS_START 0x00000000 1445 #define MVEA_REGISTERS_END 0x000003EF 1446 #define MVEA_REG_DEFAULT_TABLE struct {\ 1447 IMG_UINT16 uRegOffset;\ 1448 IMG_UINT32 uRegDefault;\ 1449 IMG_UINT32 uRegMask;\ 1450 bool bReadonly;\ 1451 char* pszName;\ 1452 } MVEA_Defaults[] = {\ 1453 {0x0000, 0x00000000, 0x0000003F, 0, "CR_IMG_MVEA_SRST" } ,\ 1454 {0x0004, 0x00000000, 0xC0001FFF, 0, "CR_IMG_MVEA_INTSTAT" } ,\ 1455 {0x0008, 0x00000000, 0xC0001FFF, 0, "CR_IMG_MVEA_INTENAB" } ,\ 1456 {0x000C, 0x00000000, 0x00001FFF, 0, "CR_IMG_MVEA_INTCLEAR" } ,\ 1457 {0x0010, 0x00000000, 0x00001FFF, 0, "CR_IMG_MVEA_INT_COMB_SEL" } ,\ 1458 {0x0014, 0x00000000, 0x000000CF, 0, "CR_MVEA_START" } ,\ 1459 {0x0018, 0x00000000, 0x000001FF, 0, "CR_MVEA_BUSY" } ,\ 1460 {0x001C, 0x00000000, 0x000000FF, 0, "CR_MVEA_DMACMDFIFO_WAIT" } ,\ 1461 {0x0020, 0x00000000, 0x0000011F, 0, "CR_MVEA_DMACMDFIFO_STATUS" } ,\ 1462 {0x0024, 0x00000000, 0x0000000F, 0, "CR_MVEA_AUTO_CLOCK_GATING" } ,\ 1463 {0x0028, 0x00000000, 0x0000001F, 0, "CR_MVEA_MAN_CLOCK_GATING" } ,\ 1464 {0x002C, 0x00000000, 0x0000FFFF, 0, "CR_TOPAZ_MB_PERFORMANCE_RESULT" } ,\ 1465 {0x0030, 0x00000000, 0x003FFFFF, 0, "CR_TOPAZ_MB_PERFORMANCE_MB_NUMBER" } ,\ 1466 {0x0034, 0x00000000, 0x0000FFFF, 0, "CR_TOPAZ_HW_MB_PERFORMANCE_RESULT" } ,\ 1467 {0x0038, 0x00000000, 0x003FFFFF, 0, "CR_TOPAZ_HW_MB_PERFORMANCE_MB_NUMBER" } ,\ 1468 {0x0100, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_ESB_DIAGNOSTICS" } ,\ 1469 {0x0104, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_DMA_DIAGNOSTICS" } ,\ 1470 {0x0108, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_SIGNATURE_ENC_MEM_WDATA" } ,\ 1471 {0x010C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMC_SIGNATURE_ENC_MEM_ADDR" } ,\ 1472 {0x011C, 0x00000000, 0x0000001F, 0, "CR_CMC_PROC_ESB_ACCESS" } ,\ 1473 {0x012C, 0x00000000, 0x0000001F, 0, "CR_CMC_LRB_LOGICAL_OFFSET" } ,\ 1474 {0x0130, 0x00000000, 0x00001111, 0, "CR_SEQUENCER_SETUP" } ,\ 1475 {0x0134, 0x00000000, 0xFFFFFF3F, 0, "CR_SEQUENCER_CONTROL" } ,\ 1476 {0x0138, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_Y_ROW_ADDR" } ,\ 1477 {0x013C, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_U_ROW_ADDR" } ,\ 1478 {0x0140, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_V_ROW_ADDR" } ,\ 1479 {0x0144, 0x00000000, 0x0000FFFF, 0, "CR_CURR_MB_Y_ROW_STRIDE" } ,\ 1480 {0x0148, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_MB_UV_ROW_STRIDE" } ,\ 1481 {0x014C, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_Y_ROW_ADDR" } ,\ 1482 {0x0150, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_UV_ROW_ADDR" } ,\ 1483 {0x0154, 0x00000000, 0xFFFFFFFF, 0, "CR_REF_ROW_STRIDE" } ,\ 1484 {0x0158, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_Y_ROW_IN_ADDR" } ,\ 1485 {0x015C, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_UV_ROW_IN_ADDR" } ,\ 1486 {0x0160, 0x00000000, 0xFFFFFFFF, 0, "CR_RECON_Y_ROW_ADDR" } ,\ 1487 {0x0164, 0x00000000, 0xFFFFFFFF, 0, "CR_RECON_UV_ROW_ADDR" } ,\ 1488 {0x0168, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PARAM_ADDR" } ,\ 1489 {0x016C, 0x00000000, 0xFFFFFFFF, 0, "CR_CURR_PARAM_ADDR" } ,\ 1490 {0x0170, 0x00000000, 0xFFFFFFFF, 0, "CR_BELOW_PARAM_IN_ADDR" } ,\ 1491 {0x0174, 0x00000000, 0x00000FFF, 0, "CR_LRB_LOAD" } ,\ 1492 {0x0178, 0x00000000, 0xFFFFFFFF, 0, "CR_BELOW_PARAM_OUT_ADDR" } ,\ 1493 {0x017C, 0x00000000, 0x000FFFFF, 0, "CR_BUFFER_SIDEBAND" } ,\ 1494 {0x0180, 0x00000000, 0x00000001, 0, "CR_CMPRS_ACKNOWLEDGE" } ,\ 1495 {0x0184, 0x00000000, 0x000001FF, 0, "CR_CMPRS_SBLK_THRESHOLD" } ,\ 1496 {0x0188, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_COEFF_COST_H" } ,\ 1497 {0x018C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_COEFF_COST_L" } ,\ 1498 {0x0190, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_COEFF_THRESHOLD" } ,\ 1499 {0x0194, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_SBLK_RIGHT" } ,\ 1500 {0x0198, 0x00000000, 0x00FFFFFF, 0, "CR_CMPRS_SBLK_BOTTOM" } ,\ 1501 {0x019C, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_TRANS_CRC" } ,\ 1502 {0x01A0, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_QUANT_CRC" } ,\ 1503 {0x01A4, 0x00000000, 0xFFFFFFFF, 0, "CR_CMPRS_DIAGNOSTIC1" } ,\ 1504 {0x01A8, 0x00000000, 0x80000000, 0, "CR_CMPRS_RLE_CONTROL" } ,\ 1505 {0x01AC, 0x00000000, 0x000007FF, 0, "CR_CMPRS_RLE_STATUS" } ,\ 1506 {0x01B0, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_MAX_CYCLE_COUNT" } ,\ 1507 {0x01B4, 0x00000000, 0x303FFFFF, 0, "CR_CMPRS_MAX_CYCLE_MB" } ,\ 1508 {0x01B8, 0x00000000, 0x00000003, 0, "CR_CMPRS_MAX_CYCLE_RESET" } ,\ 1509 {0x01BC, 0x00000000, 0x0000FFFF, 0, "CR_CMPRS_VLC_CRC" } ,\ 1510 {0x01C0, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_Y_ROW_OUT_ADDR" } ,\ 1511 {0x01C4, 0x00000000, 0xFFFFFFFF, 0, "CR_ABOVE_PIX_UV_ROW_OUT_ADDR" } ,\ 1512 {0x01F0, 0x00000000, 0x007FFFFF, 0, "CR_IPE_LAMBDA_TABLE" } ,\ 1513 {0x01F4, 0x00000000, 0x00007FFF, 0, "CR_IPE_MV_BIAS_TABLE" } ,\ 1514 {0x01FC, 0x00000000, 0x000000FF, 0, "CR_IPE_QP" } ,\ 1515 {0x0200, 0x00000000, 0x00007FFF, 0, "CR_IPE_CONTROL" } ,\ 1516 {0x0204, 0x00000000, 0x00000007, 0, "CR_IPE_SEARCH_STATUS" } ,\ 1517 {0x0208, 0x00000000, 0x0000FFFF, 0, "CR_IPE_INT_MVCOST" } ,\ 1518 {0x020C, 0x00000000, 0x0000FFFF, 0, "CR_IPE_MB_SAD" } ,\ 1519 {0x0210, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_DIAG1" } ,\ 1520 {0x0214, 0x00000000, 0x0000FFFF, 0, "CR_IPE_QP_SLICE" } ,\ 1521 {0x0218, 0x00000000, 0x00000003, 0, "CR_IPE_JITTER_FACTOR" } ,\ 1522 {0x0264, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_CTRL_CRC" } ,\ 1523 {0x0268, 0x00000000, 0xFFFFFFFF, 0, "CR_IPE_WDATA_CRC" } ,\ 1524 {0x026C, 0x00000000, 0x00000001, 0, "CR_IPE_MB_PERFORMANCE_CLEAR" } ,\ 1525 {0x0270, 0x00000000, 0x0000FFFF, 1, "CR_IPE_MB_PERFORMANCE_RESULT" } ,\ 1526 {0x0274, 0x00000000, 0x003FFFFF, 1, "CR_IPE_MB_PERFORMANCE_MB_NUMBER" } ,\ 1527 {0x0278, 0x00000000, 0x0000FFFF, 0, "CR_IPE_VECTOR_CLIPPING" } ,\ 1528 {0x0280, 0x00008000, 0x01F08003, 0, "CR_JMCOMP_CONTROL" } ,\ 1529 {0x0284, 0x00000000, 0x000FFFFF, 0, "CR_JMCOMP_JPEG_BLOCK_TYPES" } ,\ 1530 {0x0288, 0x00000000, 0x00000FFF, 0, "CR_JMCOMP_JPEG_LUMA_PRED" } ,\ 1531 {0x028C, 0x00000000, 0x0FFF0FFF, 0, "CR_JMCOMP_JPEG_CHROMA_PREDS" } ,\ 1532 {0x0314, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CRC" } ,\ 1533 {0x0318, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_VLC_CRC" } ,\ 1534 {0x031C, 0x00000000, 0x0003FFFF, 0, "CR_JMCOMP_PERFORMANCE_0" } ,\ 1535 {0x0320, 0x00000000, 0x003FFFFF, 0, "CR_JMCOMP_PERFORMANCE_1" } ,\ 1536 {0x0324, 0x00000000, 0x00000003, 0, "CR_JMCOMP_PERFORMANCE_2" } ,\ 1537 {0x0348, 0x00000000, 0x000001FF, 0, "CR_JMCOMP_QP_VALUE" } ,\ 1538 {0x0370, 0x00000000, 0x0000001F, 0, "CR_SPE_ZERO_THRESH" } ,\ 1539 {0x0374, 0x00000000, 0x0003FFFF, 0, "CR_SPE_INTRA16_BIAS_TABLE" } ,\ 1540 {0x0378, 0x00000000, 0x0003FFFF, 0, "CR_SPE_INTER_BIAS_TABLE" } ,\ 1541 {0x037C, 0x00000000, 0x00007FFF, 0, "CR_SPE_PRED_VECTOR_BIAS_TABLE" } ,\ 1542 {0x0380, 0x00000000, 0x0000001F, 0, "CR_SPE_CONTROL" } ,\ 1543 {0x0384, 0x00000000, 0x0001FFFF, 0, "CR_SPE_INTRA_COST" } ,\ 1544 {0x038C, 0x00000000, 0x00000001, 0, "CR_SPE_REQUEST" } ,\ 1545 {0x0390, 0x00000000, 0x0000FFFF, 0, "CR_SPE_INTER_SUM_MIN_SADS" } ,\ 1546 {0x0394, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_DIAGNOSTIC1" } ,\ 1547 {0x0398, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_INTER_SAD_SIGNATURE" } ,\ 1548 {0x039C, 0x00000000, 0xFFFFFFFF, 0, "CR_SPE_INTRA_SAD_SIGNATURE" } ,\ 1549 {0x03A0, 0x003CFFC2, 0xFFFFFFFF, 0, "CR_SPE_MVD_CLIP_RANGE" } ,\ 1550 {0x03A4, 0x00000000, 0x0000FFFF, 1, "CR_SPE_INT_MVCOST" } ,\ 1551 {0x03B0, 0x00000000, 0xFFFFFFFF, 0, "CR_IMG_MVEA_RSVD0" } ,\ 1552 {0x03B4, 0x00000000, 0x0000007F, 0, "CR_MVEA_CRC_RESET" } ,\ 1553 {0x03BC, 0x00000000, 0x03FF03FF, 0, "CR_SPE_MB_COUNT" } ,\ 1554 {0x03D4, 0x00000000, 0x7FFF7FFF, 0, "CR_SPE_PRED_VECTOR" } ,\ 1555 {0x03D8, 0x00000000, 0x0000FFFF, 0, "CR_SPE_MAX_CYCLE_COUNT" } ,\ 1556 {0x03DC, 0x00000000, 0xC03FFFFF, 0, "CR_SPE_MAX_CYCLE_MB" } ,\ 1557 {0x03E0, 0x00000000, 0x0000FFFF, 0, "CR_SPE_INTRA_SUM_MIN_SADS" } ,\ 1558 {0x03E4, 0x00000000, 0x00000001, 0, "CR_SPE_MAX_CYCLE_RESET" } ,\ 1559 {0x03E8, 0x00000000, 0x0000FFFF, 0, "CR_SEQUENCER_SYNC" } ,\ 1560 {0x03EC, 0x00000000, 0x0000FFFF, 1, "CR_IPE_SKIPPED_MV" } ,\ 1561 {0x02D0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_0" },\ 1562 {0x02D4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_1" },\ 1563 {0x02D8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_2" },\ 1564 {0x02DC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_3" },\ 1565 {0x02E0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_4" },\ 1566 {0x02E4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_5" },\ 1567 {0x02E8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_6" },\ 1568 {0x02EC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_7" },\ 1569 {0x02F0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_8" },\ 1570 {0x02F4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_9" },\ 1571 {0x02F8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_10" },\ 1572 {0x02FC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_11" },\ 1573 {0x0300, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_12" },\ 1574 {0x0304, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_13" },\ 1575 {0x0308, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_14" },\ 1576 {0x030C, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_CHROMA_QUANTISER_15" },\ 1577 {0x0290, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_0" },\ 1578 {0x0294, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_1" },\ 1579 {0x0298, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_2" },\ 1580 {0x029C, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_3" },\ 1581 {0x02A0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_4" },\ 1582 {0x02A4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_5" },\ 1583 {0x02A8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_6" },\ 1584 {0x02AC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_7" },\ 1585 {0x02B0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_8" },\ 1586 {0x02B4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_9" },\ 1587 {0x02B8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_10" },\ 1588 {0x02BC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_11" },\ 1589 {0x02C0, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_12" },\ 1590 {0x02C4, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_13" },\ 1591 {0x02C8, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_14" },\ 1592 {0x02CC, 0x00000000, 0xFFFFFFFF, 0, "CR_JMCOMP_LUMA_QUANTISER_15" },\ 1593 {0x0080, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_0" },\ 1594 {0x0084, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_1" },\ 1595 {0x0088, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_2" },\ 1596 {0x008C, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_3" },\ 1597 {0x0090, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_4" },\ 1598 {0x0094, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_5" },\ 1599 {0x0098, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_6" },\ 1600 {0x009C, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_7" },\ 1601 {0x00A0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_8" },\ 1602 {0x00A4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_9" },\ 1603 {0x00A8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_10" },\ 1604 {0x00AC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_11" },\ 1605 {0x00B0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_12" },\ 1606 {0x00B4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_13" },\ 1607 {0x00B8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_14" },\ 1608 {0x00BC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_15" },\ 1609 {0x00C0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_16" },\ 1610 {0x00C4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_17" },\ 1611 {0x00C8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_18" },\ 1612 {0x00CC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_19" },\ 1613 {0x00D0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_20" },\ 1614 {0x00D4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_21" },\ 1615 {0x00D8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_22" },\ 1616 {0x00DC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_23" },\ 1617 {0x00E0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_24" },\ 1618 {0x00E4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_25" },\ 1619 {0x00E8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_26" },\ 1620 {0x00EC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_27" },\ 1621 {0x00F0, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_28" },\ 1622 {0x00F4, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_29" },\ 1623 {0x00F8, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_30" },\ 1624 {0x00FC, 0x00000000, 0xE0FFFFFF, 0, "CR_CMC_ESB_LOGICAL_REGION_SETUP_31" },\ 1625 { 0 }} 1626 1627 #define MVEA_REGS_INIT(uBase) \ 1628 { \ 1629 int n;\ 1630 MVEA_REG_DEFAULT_TABLE;\ 1631 for (n = 0; n < sizeof(MVEA_Defaults)/ sizeof(MVEA_Defaults[0] ) -1; n++)\ 1632 {\ 1633 RegWriteNoTrap(MVEA_Defaults[n].uRegOffset + uBase, MVEA_Defaults[n].uRegDefault); \ 1634 }\ 1635 } 1636
