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--> 23 <div id="titlearea"> 24 <table cellspacing="0" cellpadding="0"> 25 <tbody> 26 <tr style="height: 56px;"> 27 <td style="padding-left: 0.5em;"> 28 <div id="projectname">NDK Programmer's Guide 29 </div> 30 </td> 31 </tr> 32 </tbody> 33 </table> 34 </div> 35 <!-- end header part --> 36 <!-- Generated by Doxygen 1.8.5 --> 37 </div><!-- top --> 38 <div id="side-nav" class="ui-resizable side-nav-resizable"> 39 <div id="nav-tree"> 40 <div id="nav-tree-contents"> 41 <div id="nav-sync" class="sync"></div> 42 </div> 43 </div> 44 <div id="splitbar" style="-moz-user-select:none;" 45 class="ui-resizable-handle"> 46 </div> 47 </div> 48 <script type="text/javascript"> 49 $(document).ready(function(){initNavTree('md_3__key__topics__c_p_u__support__chapter_1-section_8__a_b_is.html','');}); 50 </script> 51 <div id="doc-content"> 52 <div class="header"> 53 <div class="headertitle"> 54 <div class="title">ABI Management </div> </div> 55 </div><!--header--> 56 <div class="contents"> 57 <div class="textblock"><p><a href="#intro">Introduction</a><br/> 58 <a href="#sa">Supported ABIs</a><br/> 59 <a href="#gc">Generating code for a Specific ABI</a><br/> 60 <a href="#am">ABI management on the Android Platform</a><br/> 61 </p> 62 <p><a class="anchor" id="intro"></a> </p> 63 <h2>Introduction</h2> 64 <p>Every piece of native code generated with the Android NDK matches a given 65 application binary interface ("ABI") that defines exactly how your 66 application's machine code is expected to interact with the system at 67 runtime.</p> 68 <p>A typical ABI describes things in <em>excruciating</em> detail, and 69 typically includes the following information:</p> 70 <ul> 71 <li>The CPU instruction set that the machine code should use.</li> 72 <li>The endianness of memory stores and loads at runtime.</li> 73 <li>The format of executable binaries (shared libraries, programs, etc.), and 74 the types of content they support.</li> 75 <li>Various conventions used to pass data between your code and the system. 76 These include alignment constraints, as well as how registers and/or the stack 77 are used when functions are called.</li> 78 <li>Alignment and size constraints for enum types, structure fields, and 79 arrays.</li> 80 <li>The list of function symbols available to your machine code at runtime, 81 generally from a very specifically selected set of libraries.</li> 82 </ul> 83 <p>This document lists the exact ABIs supported by the Android NDK and the 84 official Android platform releases.</p> 85 <p><a class="anchor" id="sa"></a> </p> 86 <h2>Supported ABIs</h2> 87 <h3>Overview</h3> 88 <p>Table 1 provides an at-a-glance overview of each ABI's supported instruction 89 sets and capabilities.</p> 90 <table class="doxtable"> 91 <tr> 92 <th></th><th>Instruction Set(s) </th><th>Notes </th></tr> 93 <tr> 94 <td><a href="#armeabi">armeabi</a> </td><td>ARMV5TE and later<br/> 95 Thumb-1 </td><td><b>No</b> hard float.</td></tr> 96 <tr> 97 <td><a href="#v7a">armeabi-v7a</a> </td><td>armeabi<br/> 98 Thumb-2<br/> 99 VFPv3-D16<br/> 100 other optional </td><td>Hard float when specified as 101 <code>armeabi-v7a-hard</code>.<br/> 102 Incompatible with ARMv5, v6 devices.</td></tr> 103 <tr> 104 <td><a href="#arm64-v8a">arm64-v8a</a> </td><td>AArch-64</td><td></td></tr> 105 <tr> 106 <td><a href="#x86">x86</a> </td><td>x86 (IA-32)<br/> 107 MMX<br/> 108 SSE/2/3<br> 109 SSSE3</td><td>No support for MOVBE or SSE4.</td></tr> 110 <tr> 111 <td><a href="#86-64">x86_64</a> </td><td>x86-64<br/> 112 MMX<br/> 113 SSE/2/3<br> 114 SSSE3<br> 115 SSE4.1, 4.2<br> 116 POPCNT</td><td></td></tr> 117 <tr> 118 <td><a href="#mips">mips</a></td><td>MIPS32r1 and later</td><td>Hard 119 float.</td></tr> 120 <tr> 121 <td><a href="#mips64">mips 64</a></td><td>MIPS64r6</td><td></td></tr> 122 </table> 123 <p><b>Table 1.</b> Respective ABI capabilities</p> 124 <p>More detailed information about each ABI appears below.</p> 125 <p><a class="anchor" id="armeabi"></a> </p> 126 <h3>armeabi</h3> 127 <p>This is the name of an ABI for ARM-based CPUs that support <em>at least</em> 128 the ARMv5TE instruction set. Please refer to the following documentation for 129 more details:</p> 130 <ul> 131 <li><a href="https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf">ARM Architecture 132 Reference Manual</a> ("ARMARM")</li> 133 <li><a 134 href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042e/IHI0042E_aapcs.p 135 df">Procedure Call Standard for the ARM Architecture</a> ("AAPCS")</li> 136 <li><a 137 href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0101a/DUI0101A_Elf.pdf 138 ">ARM ELF File Format</a> ("ARMELF")</li> 139 <li><a 140 href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.swdev.a 141 bi/index.html">Application Binary Interface (ABI) for the ARM Architecture</a> 142 ("BSABI")</li> 143 <li><a 144 href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0037c/IHI0037C_bpabi.p 145 df">Base Platform ABI for the ARM Architecture</a> ("BPABI")</li> 146 <li><a 147 href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0039c/IHI0039C_clibabi 148 .pdf">C Library ABI for the ARM Architecture</a> ("CLIABI")</li> 149 <li><a 150 href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0041d/index 151 .html">C++ ABI for the ARM Architecture</a> ("CPPABI")</li> 152 <li><a 153 href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043d/IHI0043D_rtabi.p 154 df">Run-time ABI for the ARM Architecture</a> ("RTABI")</li> 155 <li><a href="http://www.sco.com/developers/gabi/2001-04-24/contents.html">ELF 156 System V Application Binary Interface</a> (DRAFT 2001)</li> 157 <li><a href="http://mentorembedded.github.com/cxx-abi/abi.html">Generic C++ 158 ABI</a></li> 159 </ul> 160 <p>Note that the AAPCS standard defines EABI as a <em>family</em> of similar 161 but distinct ABIs. Also, Android follows the little-endian ARM GNU/Linux ABI as 162 documented in the <a 163 href="http://sourcery.mentor.com/sgpp/lite/arm/portal/kbattach142/arm_gnu_linux_ 164 abi.pdf">ARM GNU/Linux Application Binary Interface Supplement</a></p> 165 <p>This ABI does <em>not</em> support hardware-assisted floating point 166 computations. Instead, all floating-point operations use software helper 167 functions from the compiler's <code>libgcc.a</code> static library.</p> 168 <p>The armeabi ABI supports ARMs <a 169 href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0210c/CACBC 170 AAE.html">Thumb (a.k.a. Thumb-1) instruction set</a>. The NDK generates Thumb 171 code by default unless you specify different behavior using the 172 <code>LOCAL_ARM_MODE</code> variable in your <code>Android.mk</code> file (see 173 the <a 174 href="./md_3__key__topics__building__chapter_1-section_8__android_8mk.html">Andr 175 oid.mk section</a> for details).</p> 176 <p><a class="anchor" id="v7a"></a> </p> 177 <h3>armeabi-v7a (armeabi-v7a-hard)</h3> 178 <p>armeabi-v7a <em>extends</em> armeabi to include a few CPU instruction set 179 extensions as described in the following document:</p> 180 <ul> 181 <li><a 182 href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index 183 .html">ARM Architecture v7-a Reference Manual</a></li> 184 </ul> 185 <p>The instruction extensions supported by this Android-specific ABI are:</p> 186 <ul> 187 <li>The Thumb-2 instruction set extension.</li> 188 <li>The VFP hardware FPU instructions. More specifically, VFPv3-D16, which 189 corresponds to 16 dedicated 64-bit floating point registers provided by the 190 CPU.</li> 191 </ul> 192 <p>Other extensions described by the v7-a ARM, like <a 193 href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Beijf 194 cja.html">Advanced SIMD</a> (a.k.a. NEON), VFPv3-D32, or ThumbEE are optional 195 to this ABI. This means that developers should check <em>at runtime</em> 196 whether the extensions are available. If not, they must use alternative code 197 paths. This check is similar to the one typically performed to check/use <a 198 href="http://en.wikipedia.org/wiki/MMX_(instruction_set">MMX</a>), <a 199 href="http://en.wikipedia.org/wiki/SSE2">SSE2</a> and other specialized 200 instruction sets on x86 CPUs.</p> 201 <p>For information about how to perform these runtime checks, refer to <a 202 href="./md_3__key__topics__c_p_u__support__c_p_u-_f_e_a_t_u_r_e_s.html">CPU 203 Features</a>. Also, for information about the NDK's support for building 204 NEON-capable machine code, see <a 205 href="md_3__key__topics__c_p_u__support__c_p_u-_a_r_m-_n_e_o_n.html">CPU-ARM-NEO 206 N</a>.</p> 207 <p>Note that armeabi-v7a uses the <code>-mfloat-abi=softfp</code> switch to 208 enforce the rule that all double values must be passed during function calls in 209 "core" register pairs, instead of dedicated FP ones. All internal computations 210 can be performed, however, with the FP registers, which speeds them up 211 greatly.</p> 212 <p>Although this constraint results in a modest performance hit, it ensures 213 compatibility with all existing armeabi binaries. If you need the additional 214 performance, you can specify your ABI as armeabi-v7a-hard instead. Doing so 215 allows you to use hard floats, while still linking with Android native APIs 216 that use <code>softfp</code>. For more information, look inside the 217 <code>Android.mk</code> file in <code>/tests/device/hard-float/jni/</code>.</p> 218 <p><b>NOTE:</b> The armeabi-v7a machine code does <em>not</em> run on ARMv5 or 219 ARMv6 based devices.</p> 220 <p><b>NOTE:</b> You cannot specify <code>APP_ABI</code> as both armeabi-v7a and 221 armeabi-v7a-hard. In either case, the build system places the shared libraries 222 in the <code>armeabi-v7a/</code> directory.</p> 223 <p><a class="anchor" id="hard"></a> </p> 224 <h3>armeabi-v7a-hard</h3> 225 <p>This variant of the armeabi-v7a ABI is unique to the NDK. The NDK build 226 system adds the following flags in addition to those that it uses for the 227 armeabi-v7a ABI. </p> 228 <pre class="fragment">TARGET_CFLAGS += -mhard-float -D_NDK_MATH_NO_SOFTFP=1 229 TARGET_LDFLAGS += -Wl,--no-warn-mismatch -lm_hard 230 </pre><p>All code is compiled with hard-float and linked with libm_hard.a. This 231 is the same math library as libm.a, except that it follows hard-float ABI 232 conventions. The generated shared libraries are stored in 233 <code>lib/armeabi-v7a/</code>.</p> 234 <p><a class="anchor" id="arm64-v8a"></a> </p> 235 <h3>arm64-v8a</h3> 236 <p>This ABI is for ARMv8-based CPUs that support AArch64.</p> 237 <p>For more information, see the <a 238 href="http://www.arm.com/files/downloads/ARMv8_Architecture.pdf">ARMv8 239 Technology Preview</a>, and contact ARM for further details.</p> 240 <p><a class="anchor" id="x86"></a> </p> 241 <h3>x86</h3> 242 <p>This is the name of an ABI for CPUs supporting the instruction set commonly 243 referred to as "x86" or "IA-32". Characteristics of this ABI include:</p> 244 <ul> 245 <li>instructions normally generated by GCC with the following compiler 246 flags:</li> 247 </ul> 248 <pre class="fragment">-march=i686 -mtune=intel -mssse3 -mfpmath=sse -m32 249 </pre><p>These flags target the the Pentium Pro instruction set, along with the 250 the MMX, <a 251 href="http://en.wikipedia.org/wiki/Streaming_SIMD_Extensions">SSE</a>, SSE2, <a 252 href="http://en.wikipedia.org/wiki/SSE3">SSE3</a>, and <a 253 href="http://en.wikipedia.org/wiki/SSSE3">SSSE3</a> instruction set extensions. 254 The generated code is a balanced optimization across the top Intel 32-bit 255 CPUs.</p> 256 <p><b>NOTE:</b> The compiler flags shown above do not represent a comprehensive 257 list. In particular, they do not include compiler optimization options used by 258 default and/or recommended for x86 performance improvement. For performance 259 optimization hints on x86 GCC, refer to Intel's article titled <a 260 href="http://software.intel.com/blogs/2012/09/26/gcc-x86-performance-hints">GCC 261 x86 Performance</a>. Also, to investigate what other flags may be useful, 262 especially <code>-f*</code> and <code>-m</code>, see <a 263 href="https://gcc.gnu.org/onlinedocs/gcc/i386-and-x86-64-Options.html#i386-and-x 264 86-64-Options">GCC online documentation: Intel 386 and AMD x86-64 265 Options</a>.</p> 266 <ul> 267 <li>Use of the standard Linux x86 32-bit calling convention, as opposed to the 268 SVR4 one. (For more information, see section 6, "Register Usage" of <a 269 href="http://www.agner.org/optimize/calling_conventions.pdf">Calling 270 conventions for different C++ compilers and operating systems</a>.)</li> 271 </ul> 272 <p>The ABI does <em>not</em> include any other optional IA-32 instruction set 273 extensions, including, but not limited to:</p> 274 <ul> 275 <li>The MOVBE instruction.</li> 276 <li>Any variant of SSE4.</li> 277 </ul> 278 <p>You can still use these, as long as you use runtime feature-probing to 279 enable them, and provide fallbacks for devices that do not support them.</p> 280 <p>The NDK toolchain assumes 16 byte stack alignment. Tools and options used by 281 default enforce this rule. It is the user's responsibilty to ensure that stack 282 alignment is maintained if they write assembly code, and to ensure that other 283 compilers also obey this rule.</p> 284 <p>Please refer to the following documents for more details:</p> 285 <ul> 286 <li><a 287 href="https://gcc.gnu.org/onlinedocs/gcc/i386-and-x86-64-Options.html#i386-and-x 288 86-64-Options">GCC online documentation: Intel 386 and AMD x86-64 289 Options</a></li> 290 <li><a href="http://www.agner.org/optimize/calling_conventions.pdf">Calling 291 conventions for different C++ compilers and operating systems</a></li> 292 <li><a 293 href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia- 294 32-architectures-software-developer-instruction-set-reference-manual-325383.pdf" 295 >Intel IA-32 Intel Architecture Software Developer's Manual, Volume 2: 296 Instruction Set Reference</a></li> 297 <li><a 298 href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia- 299 32-architectures-software-developer-system-programming-manual-325384.pdf">Intel 300 IA-32 Intel Architecture Software Developer's Manual, Volume 3: System 301 Programming Guide</a></li> 302 <li>Amendment to System V Application Binary Interface: Intel386 Processor 303 Architecture Supplement</li> 304 </ul> 305 <p><a class="anchor" id="86-64"></a> </p> 306 <h3>x86_64</h3> 307 <p>This ABI is for CPUs supporting the instruction set commonly referred to as 308 "x86-64." It supports instructions normally generated by GCC with the following 309 compiler flags: </p> 310 <pre class="fragment">-march=x86-64 -msse4.2 -mpopcnt -m64 -mtune=intel 311 </pre><p>These flags target the x86-64 instruction set, according to the GCC 312 documentation. along with the MMX, SSE, SSE2, SSE3, SSSE3, <a 313 href="http://en.wikipedia.org/wiki/SSE4">SSE4.1</a>,SSE4.2, and POPCNT 314 instruction-set extensions. The generated code is a balanced optimization 315 across the top Intel 64-bit CPUs.</p> 316 <p><b>NOTE:</b> The compiler flags shown above do not represent a comprehensive 317 list. In particular, they do not include compiler optimization options used by 318 default and/or recommended for x86-64 performance improvement. For performance 319 optimization hints on x86-64 GCC, refer to Intel's article titled <a 320 href="http://software.intel.com/blogs/2012/09/26/gcc-x86-performance-hints">GCC 321 x86 Performance</a>.</p> 322 <p>The ABI does <em>not</em> include any other optional x86-64 instruction set 323 extensions, including, but not limited to:</p> 324 <ul> 325 <li>the MOVBE instruction</li> 326 <li>the SHA instruction</li> 327 <li>the AVX extension</li> 328 <li>the AVX2 extension</li> 329 </ul> 330 <p>You can still use these, as long as you use runtime feature probing to 331 enable them, and provide fallbacks for devices that do not support them.</p> 332 <p>Please refer to the following documents for more details:</p> 333 <ul> 334 <li><a href="http://www.agner.org/optimize/calling_conventions.pdf">Calling 335 conventions for different C++ compilers and operating systems</a></li> 336 <li><a 337 href="http://www.intel.com/content/www/us/en/processors/architectures-software-d 338 eveloper-manuals.html?iid=tech_vt_tech+64-32_manuals">Intel64 and IA-32 339 Architectures Software Developer's Manual, Volume 2: Instruction Set 340 Reference</a></li> 341 <li><a 342 href="http://www.intel.com/content/www/us/en/processors/architectures-software-d 343 eveloper-manuals.html?iid=tech_vt_tech+64-32_manuals">Intel64 and IA-32 Intel 344 Architecture Software Developer's Manual Volume 3: System Programming</a></li> 345 <li>Amendment to System V Application Binary Interface AMD64 Processor 346 Architecture Supplement</li> 347 </ul> 348 <p><a class="anchor" id="mips"></a> </p> 349 <h3>mips</h3> 350 <p>This ABI is for MIPS-based CPUs that support <b>at least</b> the MIPS32r1 351 instruction set. It includes the following features:</p> 352 <ul> 353 <li>MIPS32 revision 1 ISA</li> 354 <li>Little-endian</li> 355 <li>O32</li> 356 <li>Hard-float</li> 357 <li><p class="startli">No DSP application-specific extensions</p> 358 <p class="startli">For more information, please refer to the following 359 documentation.</p> 360 </li> 361 <li>ELF for the MIPS Architecture ("MIPSELF")</li> 362 <li>FAQ for MIPS Toolchains ("MIPSFAQ")</li> 363 <li>Toolchain Specifics ("MIPSTOOL")</li> 364 <li>SDE Library ("MIPSSDE")</li> 365 <li>Instruction Set Quick Reference ("MIPSISA")</li> 366 <li>Architecture for Programmers ("MIPSARCH")</li> 367 <li><a href="https://refspecs.linuxbase.org/elf/gabi4+/contents.html">ELF 368 System V Application Binary Interface: DRAFT - 24 April 2001</a></li> 369 <li><p class="startli"><a 370 href="http://sourcery.mentor.com/public/cxx-abi/abi.html">Generic C++ 371 ABI</a></p> 372 <p class="startli">The MIPS-specific documentation is available <a 373 href="http://www.imgtec.com/mips/architectures/mips32.asp">here</a>, with 374 further information <a 375 href="https://sourcery.mentor.com/sgpp/lite/mips/portal/target_arch?@action=faq& 376 amp;target_arch=MIPS">here</a>.</p> 377 </li> 378 </ul> 379 <p><b>NOTE::</b> This ABI assumes a CPU:FPU clock ratio of 2:1 for maximum 380 compatibility.</p> 381 <p><b>NOTE::</b> Neither MIPS16 nor micromips is provided.</p> 382 <p><a class="anchor" id="mips64"></a> </p> 383 <h3>mips64</h3> 384 <p>This ABI is for MIPS64 R6.</p> 385 <p><a class="anchor" id="gc"></a> </p> 386 <h2>Generating code for a specific ABI</h2> 387 <p>By default, the NDK generates machine code for the armeabi ABI. You can 388 generate ARMv7-a-compatible machine code, instead, by adding the following line 389 to your <code>Application.mk</code> file.</p> 390 <pre class="fragment"> APP_ABI := armeabi-v7a 391 </pre><p>It is also possible to build machine code for two or more distinct 392 ABIs, using spaces as delimiters. For example:</p> 393 <pre class="fragment"> APP_ABI := armeabi armeabi-v7a 394 </pre><p>This instructs the NDK to build two versions of your machine code: one 395 for each ABI listed on this line. The build system copies the libraries to your 396 application project path, and ultimately packages them into your APK, creating 397 a <a href="http://en.wikipedia.org/wiki/Fat_binary">fat binary</a>.</p> 398 <p>At installation time, the package manager unpacks only the most appropriate 399 machine code for the target device. For details, see <a href="#aen">Automatic 400 extraction of native code at install time</a>.</p> 401 <p>You can also generate machine code for all NDK-supported ABIs:</p> 402 <pre class="fragment"> APP_ABI := all 403 </pre><p>Doing so will ensure that your app package contains libraries for all 404 target ABIs. The tradeoff is that a fat binary is larger than one for a single 405 system.</p> 406 <p><a class="anchor" id="am"></a> </p> 407 <h2>ABI Management on the Android platform</h2> 408 <p>This section provides details about how the Android platform manages native 409 code in APKs.</p> 410 <h3>Native code in app packages</h3> 411 <p>Both the Play Store and Package Manager expect to find NDK-generated 412 libraries on filepaths inside the APK matching the following pattern:</p> 413 <pre class="fragment"> lib/<abi>/lib<name>.so 414 </pre><p><abi> is one of the ABI names listed in the <a 415 href="#sa">Supported ABIs</a> section of this document, and <name> is the 416 name that the app uses to load the library from the VM. For example:</p> 417 <pre class="fragment"> System.loadLibrary("<name>"); 418 </pre><p>Since APK files are just zip files, it is trivial to examine them and 419 confirm that the shared native libraries are where they belong.</p> 420 <p>If the native shared libraries are not where the system expects to find 421 them, it can't do anything with them. In such a case, the app itself has to 422 copy the libraries over, and perform <code>dlopen()</code>.</p> 423 <p>Multiple libraries can be placed into a fat binary. For example:</p> 424 <pre class="fragment"> lib/armeabi/libfoo.so 425 lib/armeabi-v7a/libfoo.so 426 lib/arm64-v8a/libfoo.so 427 lib/x86/libfoo.so 428 lib/x86_64/libfoo.so 429 lib/mips/libfoo.so 430 lib/mips64/libfoo.so 431 </pre><p><b>NOTE::</b> ARMv7-based Android devices running 4.0.3 or earlier 432 install native libraries from the 'armeabi' directory instead of the 433 'armeabi-v7a' directory if both exist. <code>lib/armeabi</code> is listed after 434 <code>lib/armeabi-v7a</code> in APK. This issue is fixed from 4.0.4.</p> 435 <h3>Android Platform ABI support</h3> 436 <p>The Android system knows at runtime which ABI(s) it supports, because either 437 one or two build-specific system properties indicate:</p> 438 <ul> 439 <li>The "primary" ABI for the device, corresponding to the machine code used in 440 the system image itself.</li> 441 <li>An optional "secondary" ABI, corresponding to another ABI that is also 442 supported by the system image.</li> 443 </ul> 444 <p>To achieve the best performance for your NDK component, you should compile 445 directly for the primary ABI.</p> 446 <p>For example, a typical ARMv5TE-based device would only define the primary 447 ABI: armeabi. By contrast, a typical ARMv7-based device would define the 448 primary ABI as armeabi-v7a and the secondary one as armeabi, since it can run 449 application native binaries generated for each of them.</p> 450 <p>Many x86-based devices can also run armeabi-v7a and armeabi NDK binaries, 451 and defining the primary ABI as x86 and the secondary one as armeabi-v7a.</p> 452 <p>A typical MIPS-based device only defines a primary abi: mips.</p> 453 <p><a class="anchor" id="aen"></a> </p> 454 <h3>Automatic extraction of native code at install time</h3> 455 <p>When installing an application, the package manager service scans the APK, 456 and looks for any shared library of the form:</p> 457 <pre class="fragment"> lib/<primary-abi>/lib<name>.so 458 </pre><p>If none is found, and a secondary ABI is defined, the service scans 459 for shared libraries of the form: </p> 460 <pre class="fragment"> lib/<secondary-abi>/lib<name>.so 461 </pre><p>When it finds libraries that it's looking for, the package manager 462 copies them to <code>/lib/lib<name>.so</code>, under the application's 463 data directory (<code>/data/data/<package_name>/lib/</code>). If there is 464 no <code>.so</code> file, the application builds and installs, but crashes at 465 runtime.</p> 466 <p>This mechanism ensures that the system extracts the best machine code from 467 the package at installation time. </p> 468 </div></div><!-- contents --> 469 </div><!-- doc-content --> 470 <!-- start footer part --> 471 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> 472 <ul> 473 <li class="footer">Generated on Wed Jun 25 2014 00:51:19 for NDK 474 Programmer's Guide by 475 <a href="http://www.doxygen.org/index.html"> 476 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.5 </li> 477 </ul> 478 </div> 479 </body> 480 </html> 481
