Lines Matching defs:Opcode
117 /// rotate and mask opcode and mask operation.
188 /// Reg in an asm, because the load or store opcode would have to change.
456 // opcode and that it has a immediate integer right operand.
485 unsigned Opcode = N->getOpcode();
490 if (Opcode == ISD::SHL) {
495 } else if (Opcode == ISD::SRL) {
502 } else if (Opcode == ISD::ROTL) {
2502 unsigned Opcode;
2509 case MVT::f64: Opcode = PPC::LFDU; break;
2510 case MVT::f32: Opcode = PPC::LFSU; break;
2511 case MVT::i32: Opcode = PPC::LWZU; break;
2512 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2514 case MVT::i8: Opcode = PPC::LBZU; break;
2521 case MVT::i64: Opcode = PPC::LDU; break;
2522 case MVT::i32: Opcode = PPC::LWZU8; break;
2523 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2525 case MVT::i8: Opcode = PPC::LBZU8; break;
2534 Opcode, dl, LD->getValueType(0),
2538 unsigned Opcode;
2545 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
2546 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
2547 case MVT::f64: Opcode = PPC::LFDUX; break;
2548 case MVT::f32: Opcode = PPC::LFSUX; break;
2549 case MVT::i32: Opcode = PPC::LWZUX; break;
2550 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2552 case MVT::i8: Opcode = PPC::LBZUX; break;
2560 case MVT::i64: Opcode = PPC::LDUX; break;
2561 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2562 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2564 case MVT::i8: Opcode = PPC::LBZUX8; break;
2573 Opcode, dl, LD->getValueType(0),
2724 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2725 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
3495 unsigned Opcode = MachineNode->getMachineOpcode();
3496 switch (Opcode) {
3545 switch (Opcode) {
3857 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
4274 // inferred from the opcode; when we process it in the AsmPrinter,
