Lines Matching refs:Constraint
548 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
549 if (Constraint.size() == 1) {
550 switch (Constraint[0]) {
576 return TargetLowering::getConstraintType(Constraint);
581 const char *constraint) const {
589 // Look at the constraint type.
590 switch (*constraint) {
592 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
641 // Parse a "{tNNN}" register constraint for which the register type "t"
645 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
647 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
648 if (isdigit(Constraint[2])) {
651 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
660 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
661 if (Constraint.size() == 1) {
662 // GCC Constraint Letters
663 switch (Constraint[0]) {
691 if (Constraint.size() > 0 && Constraint[0] == '{') {
696 if (Constraint[1] == 'r') {
698 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
701 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
703 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
706 if (Constraint[1] == 'f') {
708 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
711 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
713 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
717 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
721 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
725 if (Constraint.length() == 1) {
726 switch (Constraint[0]) {
763 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
