Lines Matching refs:OPCODE
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
50 // The opcode that should be used to compare Op0 and Op1.
51 unsigned Opcode;
56 // The mask of CC values that Opcode can produce.
267 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
268 if (getOperationAction(Opcode, VT) == Legal)
269 setOperationAction(Opcode, VT, Expand);
1244 // as its only (other) argument. Provide the associated SystemZISD opcode and
1246 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1251 Opcode = SystemZISD::TBEGIN;
1256 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1261 Opcode = SystemZISD::TEND;
1272 // opcode and the mask of valid CC values if so.
1273 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1279 Opcode = SystemZISD::PACKS_CC;
1286 Opcode = SystemZISD::PACKLS_CC;
1294 Opcode = SystemZISD::VICMPES;
1302 Opcode = SystemZISD::VICMPHS;
1310 Opcode = SystemZISD::VICMPHLS;
1315 Opcode = SystemZISD::VTM;
1322 Opcode = SystemZISD::VFAE_CC;
1329 Opcode = SystemZISD::VFAEZ_CC;
1336 Opcode = SystemZISD::VFEE_CC;
1343 Opcode = SystemZISD::VFEEZ_CC;
1350 Opcode = SystemZISD::VFENE_CC;
1357 Opcode = SystemZISD::VFENEZ_CC;
1364 Opcode = SystemZISD::VISTR_CC;
1371 Opcode = SystemZISD::VSTRC_CC;
1378 Opcode = SystemZISD::VSTRCZ_CC;
1383 Opcode = SystemZISD::VFCMPES;
1388 Opcode = SystemZISD::VFCMPHS;
1393 Opcode = SystemZISD::VFCMPHES;
1398 Opcode = SystemZISD::VFTCI;
1409 unsigned Opcode) {
1420 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1429 unsigned Opcode) {
1438 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1441 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1822 // a comparison of type Opcode between the AND result and CmpVal.
1991 C.Opcode = SystemZISD::TM;
2003 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2005 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2009 C.Opcode = Opcode;
2042 unsigned Opcode, CCValid;
2045 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2046 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2049 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2050 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2056 C.Opcode = SystemZISD::FCMP;
2060 C.Opcode = SystemZISD::ICMP;
2097 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2100 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2107 if (C.Opcode == SystemZISD::ICMP)
2110 if (C.Opcode == SystemZISD::TM) {
2116 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2136 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2140 unsigned Extend, unsigned Opcode,
2144 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2207 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2209 return Opcode;
2213 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2215 return Opcode;
2230 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2232 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, SDLoc DL,
2241 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2242 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2245 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2283 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2284 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2287 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2288 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2368 if (C.Opcode == SystemZISD::ICMP &&
2453 unsigned Opcode,
2491 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2864 unsigned Opcode;
2869 Opcode = SystemZISD::SDIVREM32;
2872 Opcode = SystemZISD::SDIVREM32;
2874 Opcode = SystemZISD::SDIVREM64;
2880 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
3056 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3059 unsigned Opcode) const {
3077 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3079 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3103 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3106 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3107 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3115 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3261 unsigned Opcode, CCValid;
3262 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3264 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3276 unsigned Opcode, CCValid;
3277 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3278 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3335 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3336 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3340 unsigned Opcode;
3560 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3561 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3569 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3572 } else if (P.Opcode == SystemZISD::PACK) {
3577 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
4420 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4421 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4422 switch ((SystemZISD::NodeType)Opcode) {
4424 OPCODE(RET_FLAG);
4425 OPCODE(CALL);
4426 OPCODE(SIBCALL);
4427 OPCODE(TLS_GDCALL);
4428 OPCODE(TLS_LDCALL);
4429 OPCODE(PCREL_WRAPPER);
4430 OPCODE(PCREL_OFFSET);
4431 OPCODE(IABS);
4432 OPCODE(ICMP);
4433 OPCODE(FCMP);
4434 OPCODE(TM);
4435 OPCODE(BR_CCMASK);
4436 OPCODE(SELECT_CCMASK);
4437 OPCODE(ADJDYNALLOC);
4438 OPCODE(EXTRACT_ACCESS);
4439 OPCODE(POPCNT);
4440 OPCODE(UMUL_LOHI64);
4441 OPCODE(SDIVREM32);
4442 OPCODE(SDIVREM64);
4443 OPCODE(UDIVREM32);
4444 OPCODE(UDIVREM64);
4445 OPCODE(MVC);
4446 OPCODE(MVC_LOOP);
4447 OPCODE(NC);
4448 OPCODE(NC_LOOP);
4449 OPCODE(OC);
4450 OPCODE(OC_LOOP);
4451 OPCODE(XC);
4452 OPCODE(XC_LOOP);
4453 OPCODE(CLC);
4454 OPCODE(CLC_LOOP);
4455 OPCODE(STPCPY);
4456 OPCODE(STRCMP);
4457 OPCODE(SEARCH_STRING);
4458 OPCODE(IPM);
4459 OPCODE(SERIALIZE);
4460 OPCODE(TBEGIN);
4461 OPCODE(TBEGIN_NOFLOAT);
4462 OPCODE(TEND);
4463 OPCODE(BYTE_MASK);
4464 OPCODE(ROTATE_MASK);
4465 OPCODE(REPLICATE);
4466 OPCODE(JOIN_DWORDS);
4467 OPCODE(SPLAT);
4468 OPCODE(MERGE_HIGH);
4469 OPCODE(MERGE_LOW);
4470 OPCODE(SHL_DOUBLE);
4471 OPCODE(PERMUTE_DWORDS);
4472 OPCODE(PERMUTE);
4473 OPCODE(PACK);
4474 OPCODE(PACKS_CC);
4475 OPCODE(PACKLS_CC);
4476 OPCODE(UNPACK_HIGH);
4477 OPCODE(UNPACKL_HIGH);
4478 OPCODE(UNPACK_LOW);
4479 OPCODE(UNPACKL_LOW);
4480 OPCODE(VSHL_BY_SCALAR);
4481 OPCODE(VSRL_BY_SCALAR);
4482 OPCODE(VSRA_BY_SCALAR);
4483 OPCODE(VSUM);
4484 OPCODE(VICMPE);
4485 OPCODE(VICMPH);
4486 OPCODE(VICMPHL);
4487 OPCODE(VICMPES);
4488 OPCODE(VICMPHS);
4489 OPCODE(VICMPHLS);
4490 OPCODE(VFCMPE);
4491 OPCODE(VFCMPH);
4492 OPCODE(VFCMPHE);
4493 OPCODE(VFCMPES);
4494 OPCODE(VFCMPHS);
4495 OPCODE(VFCMPHES);
4496 OPCODE(VFTCI);
4497 OPCODE(VEXTEND);
4498 OPCODE(VROUND);
4499 OPCODE(VTM);
4500 OPCODE(VFAE_CC);
4501 OPCODE(VFAEZ_CC);
4502 OPCODE(VFEE_CC);
4503 OPCODE(VFEEZ_CC);
4504 OPCODE(VFENE_CC);
4505 OPCODE(VFENEZ_CC);
4506 OPCODE(VISTR_CC);
4507 OPCODE(VSTRC_CC);
4508 OPCODE(VSTRCZ_CC);
4509 OPCODE(ATOMIC_SWAPW);
4510 OPCODE(ATOMIC_LOADW_ADD);
4511 OPCODE(ATOMIC_LOADW_SUB);
4512 OPCODE(ATOMIC_LOADW_AND);
4513 OPCODE(ATOMIC_LOADW_OR);
4514 OPCODE(ATOMIC_LOADW_XOR);
4515 OPCODE(ATOMIC_LOADW_NAND);
4516 OPCODE(ATOMIC_LOADW_MIN);
4517 OPCODE(ATOMIC_LOADW_MAX);
4518 OPCODE(ATOMIC_LOADW_UMIN);
4519 OPCODE(ATOMIC_LOADW_UMAX);
4520 OPCODE(ATOMIC_CMP_SWAPW);
4521 OPCODE(PREFETCH);
4524 #undef OPCODE
4548 unsigned Opcode = Op.getOpcode();
4549 if (Opcode == ISD::BITCAST)
4552 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4574 } else if (Opcode == ISD::BUILD_VECTOR &&
4601 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4602 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4603 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4681 unsigned Opcode = N->getOpcode();
4682 if (Opcode == ISD::SIGN_EXTEND) {
4709 if (Opcode == SystemZISD::MERGE_HIGH ||
4710 Opcode == SystemZISD::MERGE_LOW) {
4725 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4734 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4744 if (Opcode == ISD::STORE) {
4761 if (Opcode == ISD::EXTRACT_VECTOR_ELT) {
4770 if (Opcode == SystemZISD::JOIN_DWORDS &&
4780 if (Opcode == ISD::FP_ROUND) {
4915 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
5369 unsigned Opcode) const {
5384 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5425 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5441 if (Opcode == SystemZ::MVC)
5445 BuildMI(MBB, DL, TII->get(Opcode))
5506 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5535 // Opcode until CC != 3.
5539 unsigned Opcode) const {
5582 BuildMI(MBB, DL, TII->get(Opcode))
5596 // Update TBEGIN instruction with final opcode and register clobbers.
5600 unsigned Opcode,
5606 // Update opcode.
5607 MI->setDesc(TII->get(Opcode));
5650 unsigned Opcode) const {
5665 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
