Lines Matching full:code
33 @table @code
35 @cindex @code{-mcpu=} command line option, ARM
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-r4},
123 @code{cortex-r4f},
124 @code{cortex-r5},
125 @code{cortex-r7},
126 @code{cortex-m4},
127 @code{cortex-m3},
128 @code{cortex-m1},
129 @code{cortex-m0},
130 @code{cortex-m0plus},
131 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
132 @code{i80200} (Intel XScale processor)
133 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
135 @code{xscale}.
136 The special name @code{all} may be used to allow the
141 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
142 is equivalent to specifying @code{-mcpu=ep9312}.
144 Multiple extensions may be specified, separated by a @code{+}. The
151 This is done be prepending @code{no} to the option that adds the extension.
154 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
158 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
159 @code{fp} (Floating Point Extensions for v8-A architecture),
160 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
161 @code{iwmmxt},
162 @code{iwmmxt2},
163 @code{maverick},
164 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
165 @code{os} (Operating System for v6M architecture),
166 @code{sec} (Security Extensions for v6K and v7-A architectures),
167 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
168 @code{virt} (Virtualization Extensions for v7-A architecture, implies
169 @code{idiv}),
171 @code{xscale}.
173 @cindex @code{-march=} command line option, ARM
179 @code{armv1},
180 @code{armv2},
181 @code{armv2a},
182 @code{armv2s},
183 @code{armv3},
184 @code{armv3m},
185 @code{armv4},
186 @code{armv4xm},
187 @code{armv4t},
188 @code{armv4txm},
189 @code{armv5},
190 @code{armv5t},
191 @code{armv5txm},
192 @code{armv5te},
193 @code{armv5texp},
194 @code{armv6},
195 @code{armv6j},
196 @code{armv6k},
197 @code{armv6z},
198 @code{armv6zk},
199 @code{armv6-m},
200 @code{armv6s-m},
201 @code{armv7},
202 @code{armv7-a},
203 @code{armv7ve},
204 @code{armv7-r},
205 @code{armv7-m},
206 @code{armv7e-m},
207 @code{armv8-a},
208 @code{iwmmxt}
210 @code{xscale}.
211 If both @code{-mcpu} and
212 @code{-march} are specified, the assembler will use
213 the setting for @code{-mcpu}.
216 extension options as the @code{-mcpu} option.
218 @cindex @code{-mfpu=} command line option, ARM
225 @code{softfpa},
226 @code{fpe},
227 @code{fpe2},
228 @code{fpe3},
229 @code{fpa},
230 @code{fpa10},
231 @code{fpa11},
232 @code{arm7500fe},
233 @code{softvfp},
234 @code{softvfp+vfp},
235 @code{vfp},
236 @code{vfp10},
237 @code{vfp10-r0},
238 @code{vfp9},
239 @code{vfpxd},
240 @code{vfpv2},
241 @code{vfpv3},
242 @code{vfpv3-fp16},
243 @code{vfpv3-d16},
244 @code{vfpv3-d16-fp16},
245 @code{vfpv3xd},
246 @code{vfpv3xd-d16},
247 @code{vfpv4},
248 @code{vfpv4-d16},
249 @code{fpv4-sp-d16},
250 @code{fp-armv8},
251 @code{arm1020t},
252 @code{arm1020e},
253 @code{arm1136jf-s},
254 @code{maverick},
255 @code{neon},
256 @code{neon-vfpv4},
257 @code{neon-fp-armv8},
259 @code{crypto-neon-fp-armv8}.
262 also affects the way in which the @code{.double} assembler directive behaves
263 when assembling little-endian code.
269 @cindex @code{-mthumb} command line option, ARM
273 @code{.code 16} directive.
275 @cindex @code{-mthumb-interwork} command line option, ARM
280 @cindex @code{-mimplicit-it} command line option, ARM
285 The @code{-mimplicit-it} option controls the behavior of the assembler when
288 If @code{never} is specified, such constructs cause a warning in ARM
289 code and an error in Thumb-2 code.
290 If @code{always} is specified, such constructs are accepted in both
291 ARM and Thumb-2 code, where the IT instruction is added implicitly.
292 If @code{arm} is specified, such constructs are accepted in ARM code
293 and cause an error in Thumb-2 code.
294 If @code{thumb} is specified, such constructs cause a warning in ARM
295 code and are accepted in Thumb-2 code. If you omit this option, the
296 behavior is equivalent to @code{-mimplicit-it=arm}.
298 @cindex @code{-mapcs-26} command line option, ARM
299 @cindex @code{-mapcs-32} command line option, ARM
306 @cindex @code{-matpcs} command line option, ARM
314 @cindex @code{-mapcs-float} command line option, ARM
320 @cindex @code{-mapcs-reentrant} command line option, ARM
323 This variant supports position independent code.
325 @cindex @code{-mfloat-abi=} command line option, ARM
330 @code{soft},
331 @code{softfp}
333 @code{hard}.
335 @cindex @code{-eabi=} command line option, ARM
340 @code{gnu},
341 @code{4}
343 @code{5}.
345 @cindex @code{-EB} command line option, ARM
350 @cindex @code{-EL} command line option, ARM
355 @cindex @code{-k} command line option, ARM
356 @cindex PIC code generation for ARM
359 as position-independent code (PIC).
361 @cindex @code{--fix-v4bx} command line option, ARM
363 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
366 @cindex @code{-mwarn-deprecated} command line option, ARM
372 @cindex @code{-mccs} command line option, ARM
392 instructions. The default, @code{divided}, uses the old style where
394 @code{unified} syntax, which can be selected via the @code{.syntax}
399 Immediate operands do not require a @code{#} prefix.
402 The @code{IT} instruction may appear, and if it does it is validated
404 generate machine code, in THUMB mode it does.
409 used, but only inside the scope of an @code{IT} instruction.
414 @code{divided} syntax).
417 The @code{.N} and @code{.W} suffixes are recognized and honored.
420 All instructions set the flags if and only if they have an @code{s}
473 @code{GOT},
474 @code{GOTOFF},
475 @code{TARGET1},
476 @code{TARGET2},
477 @code{SBREL},
478 @code{TLSGD},
479 @code{TLSLDM},
480 @code{TLSLDO},
481 @code{TLSDESC},
482 @code{TLSCALL},
483 @code{GOTTPOFF},
484 @code{GOT_PREL}
486 @code{TPOFF}.
489 @code{(PLT)} after branch targets. On legacy targets this will
531 @table @code
535 @cindex @code{.2byte} directive, ARM
536 @cindex @code{.4byte} directive, ARM
537 @cindex @code{.8byte} directive, ARM
543 @cindex @code{.align} directive, ARM
550 @cindex @code{.arch} directive, ARM
555 Specifying @code{.arch} clears any previously selected architecture
558 @cindex @code{.arch_extension} directive, ARM
564 @code{.arch_extension} may be used multiple times to add or remove extensions
567 @cindex @code{.arm} directive, ARM
569 This performs the same action as @var{.code 32}.
573 @cindex @code{.bss} directive, ARM
575 This directive switches to the @code{.bss} section.
579 @cindex @code{.cantunwind} directive, ARM
584 @cindex @code{.code} directive, ARM
585 @item .code @code{[16|32]}
589 @cindex @code{.cpu} directive, ARM
594 Specifying @code{.cpu} clears any previously selected architecture
599 @cindex @code{.dn} and @code{.qn} directives, ARM
603 The @code{dn} and @code{qn} directives are used to create typed
626 Aliases created using @code{dn} or @code{qn} can be destroyed using
627 @code{unreq}.
631 @cindex @code{.eabi_attribute} directive, ARM
636 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
637 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
638 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
639 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
640 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
641 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
642 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
643 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
644 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
645 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
646 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
647 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
648 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
649 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
650 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
651 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
652 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
653 @code{Tag_conformance}, @code{Tag_T2EE_use},
654 @code{Tag_Virtualization_use}
656 The @var{value} is either a @code{number}, @code{"string"}, or
657 @code{number, "string"} depending on the tag.
660 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
661 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
663 @cindex @code{.even} directive, ARM
667 @cindex @code{.extend} directive, ARM
668 @cindex @code{.ldouble} directive, ARM
678 @cindex @code{.fnend} directive, ARM
688 @cindex @code{.fnstart} directive, ARM
692 @cindex @code{.force_thumb} directive, ARM
697 @cindex @code{.fpu} directive, ARM
705 @cindex @code{.handlerdata} directive, ARM
709 @code{.fnend} directive will be added to the exception table entry.
711 Must be preceded by a @code{.personality} or @code{.personalityindex}
716 @cindex @code{.inst} directive, ARM
721 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
729 See @code{.extend}.
731 @cindex @code{.ltorg} directive, ARM
736 @code{GAS} maintains a separate literal pool for each section and each
737 sub-section. The @code{.ltorg} directive will only affect the literal
741 Note - older versions of @code{GAS} would dump the current literal
747 @cindex @code{.movsp} directive, ARM
756 @cindex @code{.object_arch} directive, ARM
759 Valid values for @var{name} are the same as for the @code{.arch} directive.
760 Typically this is useful when code uses runtime detection of CPU features.
764 @cindex @code{.packed} directive, ARM
771 @cindex @code{.pad} directive, ARM
777 @cindex @code{.personality} directive, ARM
781 @cindex @code{.personalityindex} directive, ARM
786 @cindex @code{.pool} directive, ARM
793 @cindex @code{.req} directive, ARM
805 @cindex @code{.save} directive, ARM
833 @cindex @code{.setfp} directive, ARM
838 The syntax of this directive is the same as the @code{add} or @code{mov}
840 @code{sp} or mentioned in a previous @code{.movsp} directive.
850 @cindex @code{.secrel32} directive, ARM
856 @cindex @code{.syntax} directive, ARM
857 @item .syntax [@code{unified} | @code{divided}]
863 @cindex @code{.thumb} directive, ARM
865 This performs the same action as @var{.code 16}.
867 @cindex @code{.thumb_func} directive, ARM
871 the assembler and linker to generate correct code for interworking
874 directive also implies @code{.thumb}
877 targets the encoding is implicit when generating Thumb code.
879 @cindex @code{.thumb_set} directive, ARM
881 This performs the equivalent of a @code{.set} directive in that it
885 way that the @code{.thumb_func} directive does.
887 @cindex @code{.tlsdescseq} directive, ARM
895 @cindex @code{.unreq} directive, ARM
898 @code{req}, @code{dn} or @code{qn} directives. For example:
909 @cindex @code{.unwind_raw} directive, ARM
914 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
915 @code{.save @{r0@}}
919 @cindex @code{.vsave} directive, ARM
937 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
951 @code{@value{AS}} implements all the standard ARM opcodes. It also
955 @table @code
957 @cindex @code{NOP} pseudo op, ARM
966 @cindex @code{LDR reg,=<label>} pseudo op, ARM
978 @cindex @code{ADR reg,<label>} pseudo op, ARM
991 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1019 @table @code
1021 @cindex @code{$a}
1023 At the start of a region of code containing ARM instructions.
1025 @cindex @code{$t}
1027 At the start of a region of code containing THUMB instructions.
1029 @cindex @code{$d}
1036 is no need to code them yourself. Support for tagging symbols ($b,
1054 If you are writing functions in assembly code, and those functions
1058 code throws an exception, the run-time library will be unable to
1059 unwind the stack through your assembly code and your program will not
1062 To illustrate the use of these pseudo ops, we will examine the code
1078 assembly code. That is a much more complex operation and should
1082 The code generated by one particular version of G++ when compiling the
1120 we assume that the assembly code does not itself throw an exception,
1122 as the @code{bl} instruction above. At each call site, the same saved
1123 registers (including @code{lr}, which indicates the return address)
1126 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1128 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1132 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1133 @code{.pad}) matters; their exact locations are irrelevant. In the
1135 instructions. That makes it easier to understand the code, but it is
1137 of the pseudo ops other than @code{.fnend} in the same order, but
1138 immediately after @code{.fnstart}.
1140 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1143 @code{.save} pseudo op is a list of registers to save. If a register
1145 function you are writing, then your code must save the value before it
1150 exception is not thrown, the function that contains the @code{.save}
1152 done with the @code{ldmfd} instruction above.)
1155 of the function and you do not need to use the @code{.save} pseudo op
1159 might throw an exception. And, you must use the @code{.save} pseudo
1162 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1168 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1170 argument is the register that is set, which is typically @code{fp}.
1178 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1184 code that calls functions which may throw exceptions. If you need to
