/external/libchrome/base/numerics/ |
safe_conversions.h | 20 template <typename Dst, typename Src> 22 return internal::DstRangeRelationToSrcRange<Dst>(value) == 47 template <typename Dst, typename Src> 48 inline Dst checked_cast(Src value) { 49 CHECK(IsValueInRangeForNumericType<Dst>(value)); 50 return static_cast<Dst>(value); 74 template <typename Dst, 77 inline Dst saturated_cast(Src value) { 79 if (std::numeric_limits<Dst>::is_iec559) 80 return static_cast<Dst>(value) [all...] |
/external/libweave/third_party/chromium/base/numerics/ |
safe_conversions.h | 20 template <typename Dst, typename Src> 22 return internal::DstRangeRelationToSrcRange<Dst>(value) == 47 template <typename Dst, typename Src> 48 inline Dst checked_cast(Src value) { 49 CHECK(IsValueInRangeForNumericType<Dst>(value)); 50 return static_cast<Dst>(value); 74 template <typename Dst, 77 inline Dst saturated_cast(Src value) { 79 if (std::numeric_limits<Dst>::is_iec559) 80 return static_cast<Dst>(value) [all...] |
/external/llvm/include/llvm/Target/ |
CostTable.h | 46 MVT::SimpleValueType Dst; 55 int ISD, MVT Dst, MVT Src) { 59 Dst == Entry.Dst;
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
AMDGPUAsmBackend.cpp | 95 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); 96 *Dst = (Value - 4) / 4; 101 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset()); 118 *Dst = Value + 4;
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_variable.h | 46 struct rc_dst_register Dst;
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/frameworks/av/services/audiopolicy/utilities/convert/ |
convert.h | 193 typedef std::vector<DstElem> Dst; 195 static inline bool run(Src &src, Dst &dst) 198 dst.clear(); 199 dst.reserve(src.size()); 205 dst.push_back(dstElem);
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/external/llvm/lib/IR/ |
GCOV.cpp | 180 uint32_t Dst; 181 if (!Buff.readInt(Dst)) 183 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst])); 186 Blocks[Dst]->addSrcEdge(Edge); 379 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) 380 DstEdges[DstEdgeNo]->Dst.Counter += N; 411 dbgs() << Edge->Dst.Number << " (" << Edge->Count << "), ";
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/external/llvm/lib/Support/ |
ConvertUTFWrapper.cpp | 115 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); 116 UTF8 *DstEnd = Dst + Out.size(); 119 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 127 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]); 153 UTF16 *Dst = &DstUTF16[0]; 154 UTF16 *DstEnd = Dst + DstUTF16.size(); 157 ConvertUTF8toUTF16(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 165 DstUTF16.resize(Dst - &DstUTF16[0]);
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/external/llvm/lib/Target/AMDGPU/ |
SILowerI1Copies.cpp | 100 const MachineOperand &Dst = MI.getOperand(0); 104 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) 107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); 112 I1Defs.push_back(Dst.getReg()); 118 I1Defs.push_back(Dst.getReg()); 124 .addOperand(Dst) 132 .addOperand(Dst) 140 .addOperand(Dst)
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R600Packetizer.cpp | 93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 97 unsigned Dst = BI->getOperand(DstIdx).getReg(); 99 Result[Dst] = AMDGPU::PS; 104 Result[Dst] = AMDGPU::PV_X; 107 if (Dst == AMDGPU::OQAP) { 111 switch (TRI.getHWRegChan(Dst)) { 127 Result[Dst] = PVReg; 241 // Is the dst reg sequence legal ?
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SILowerControlFlow.cpp | 204 unsigned Dst = MI.getOperand(0).getReg(); 208 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) 213 .addReg(Dst); 224 unsigned Dst = MI.getOperand(0).getReg(); 227 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 238 unsigned Dst = MI.getOperand(0).getReg(); 242 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 253 unsigned Dst = MI.getOperand(0).getReg(); 257 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) 431 unsigned Dst = MI.getOperand(0).getReg() [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 115 const MCOperand &Dst = MI->getOperand(0); 125 printRegName(O, Dst.getReg()); 138 const MCOperand &Dst = MI->getOperand(0); 147 printRegName(O, Dst.getReg()); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 247 unsigned Dst = MI->getOperand(0).getReg(); 250 Use = MRI->use_instr_nodbg_begin(Dst), 283 unsigned Dst, unsigned Src, bool IsKill) { 286 Dst) 351 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); 356 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst) 363 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true);
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/external/llvm/lib/Target/Hexagon/ |
HexagonPeephole.cpp | 105 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); 139 MachineOperand &Dst = MI->getOperand(0); 141 unsigned DstReg = Dst.getReg(); 158 MachineOperand &Dst = MI->getOperand(0); 163 unsigned DstReg = Dst.getReg(); 175 MachineOperand &Dst = MI->getOperand(0); 180 unsigned DstReg = Dst.getReg(); 190 MachineOperand &Dst = MI->getOperand(0); 192 unsigned DstReg = Dst.getReg(); 208 MachineOperand &Dst = MI->getOperand(0) [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
CoreEngine.cpp | 275 ExplodedNodeSet &Dst) { 279 Dst.Add(*I); 463 ExplodedNodeSet Dst; 464 SubEng.processBranch(Cond, Term, Ctx, Pred, Dst, 467 enqueue(Dst); 475 ExplodedNodeSet Dst; 476 SubEng.processCleanupTemporaryBranch(BTE, Ctx, Pred, Dst, *(B->succ_begin()), 479 enqueue(Dst); 486 ExplodedNodeSet Dst; 487 SubEng.processStaticInitializer(DS, Ctx, Pred, Dst, [all...] |
ExprEngineCXX.cpp | 27 ExplodedNodeSet &Dst) { 28 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx); 58 ExplodedNodeSet Dst; 71 evalBind(Dst, CallExpr, Pred, ThisVal, V, true); 74 for (ExplodedNodeSet::iterator I = Dst.begin(), E = Dst.end(); 360 ExplodedNodeSet &Dst) { 396 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated, 402 ExplodedNodeSet &Dst) { 421 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated [all...] |
ExprEngineCallAndReturn.cpp | 161 ExplodedNodeSet &Dst) { 167 Dst.Add(Pred); 178 removeDead(Pred, Dst, dyn_cast<ReturnStmt>(LastSt), LCtx, 322 // CEENode -> Dst -> WorkList 335 ExplodedNodeSet Dst; 337 getCheckerManager().runCheckersForPostObjCMessage(Dst, DstPostCall, *Msg, 341 getCheckerManager().runCheckersForPostStmt(Dst, DstPostCall, CE, 344 Dst.insert(DstPostCall); 348 for (ExplodedNodeSet::iterator PSI = Dst.begin(), PSE = Dst.end() [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcInstrInfo.cpp | 353 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 355 assert(Dst && Src && "Bad sub-register"); 357 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
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/external/llvm/lib/Target/X86/ |
X86FixupLEAs.cpp | 366 const MachineOperand &Dst = MI->getOperand(0); 372 .addOperand(Dst) 382 .addOperand(Dst)
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/external/llvm/unittests/Linker/ |
LinkModulesTest.cpp | 305 auto Dst = llvm::make_unique<Module>("Linked", C); 306 ASSERT_TRUE(Dst.get()); 308 Linker::linkModules(*Dst, std::move(Src)); 312 F = &*Dst->begin(); 316 NMD = &*Dst->named_metadata_begin();
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
tgsi_parse.h | 99 struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
rc_test_helpers.c | 227 fprintf(stderr, "Failed to execute regex for dst register.\n"); 245 fprintf(stderr, "Unknown dst register file type.\n"); 254 fprintf(stderr, "Could not convert dst register index\n"); 287 DBG("Dst Reg File=%u Index=%d Writemask=%d\n", 299 struct match_info Dst; 353 tokens.Dst.String = inst_str + matches[3].rm_so; 354 tokens.Dst.Length = match_length(matches, 3); 357 dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1)); 358 strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 567 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
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/external/llvm/include/llvm/Analysis/ |
DependenceAnalysis.h | 85 Dst(Destination), 118 Instruction *getDst() const { return Dst; } 207 Instruction *Src, *Dst; 222 FullDependence(Instruction *Src, Instruction *Dst, bool LoopIndependent, 287 /// depends - Tests for a dependence between the Src and Dst instructions. 291 /// if it appears that control flow can reach from Src to Dst 294 Instruction *Dst, 350 const SCEV *Dst; 462 /// establishNestingLevels - Examines the loop nesting of the Src and Dst 479 /// ... - loops containing Src but not Dst [all...] |
/external/llvm/lib/CodeGen/ |
TailDuplication.cpp | 297 unsigned Dst = Copy->getOperand(0).getReg(); 300 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { 302 MRI->replaceRegWith(Dst, Src); [all...] |