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      1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Sparc implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcInstrInfo.h"
     15 #include "Sparc.h"
     16 #include "SparcMachineFunctionInfo.h"
     17 #include "SparcSubtarget.h"
     18 #include "llvm/ADT/STLExtras.h"
     19 #include "llvm/ADT/SmallVector.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineInstrBuilder.h"
     22 #include "llvm/CodeGen/MachineMemOperand.h"
     23 #include "llvm/CodeGen/MachineRegisterInfo.h"
     24 #include "llvm/Support/ErrorHandling.h"
     25 #include "llvm/Support/TargetRegistry.h"
     26 
     27 using namespace llvm;
     28 
     29 #define GET_INSTRINFO_CTOR_DTOR
     30 #include "SparcGenInstrInfo.inc"
     31 
     32 // Pin the vtable to this file.
     33 void SparcInstrInfo::anchor() {}
     34 
     35 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
     36     : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
     37       Subtarget(ST) {}
     38 
     39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
     40 /// load from a stack slot, return the virtual or physical register number of
     41 /// the destination along with the FrameIndex of the loaded stack slot.  If
     42 /// not, return 0.  This predicate must return 0 if the instruction has
     43 /// any side effects other than loading from the stack slot.
     44 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
     45                                              int &FrameIndex) const {
     46   if (MI->getOpcode() == SP::LDri ||
     47       MI->getOpcode() == SP::LDXri ||
     48       MI->getOpcode() == SP::LDFri ||
     49       MI->getOpcode() == SP::LDDFri ||
     50       MI->getOpcode() == SP::LDQFri) {
     51     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
     52         MI->getOperand(2).getImm() == 0) {
     53       FrameIndex = MI->getOperand(1).getIndex();
     54       return MI->getOperand(0).getReg();
     55     }
     56   }
     57   return 0;
     58 }
     59 
     60 /// isStoreToStackSlot - If the specified machine instruction is a direct
     61 /// store to a stack slot, return the virtual or physical register number of
     62 /// the source reg along with the FrameIndex of the loaded stack slot.  If
     63 /// not, return 0.  This predicate must return 0 if the instruction has
     64 /// any side effects other than storing to the stack slot.
     65 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
     66                                             int &FrameIndex) const {
     67   if (MI->getOpcode() == SP::STri ||
     68       MI->getOpcode() == SP::STXri ||
     69       MI->getOpcode() == SP::STFri ||
     70       MI->getOpcode() == SP::STDFri ||
     71       MI->getOpcode() == SP::STQFri) {
     72     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
     73         MI->getOperand(1).getImm() == 0) {
     74       FrameIndex = MI->getOperand(0).getIndex();
     75       return MI->getOperand(2).getReg();
     76     }
     77   }
     78   return 0;
     79 }
     80 
     81 static bool IsIntegerCC(unsigned CC)
     82 {
     83   return  (CC <= SPCC::ICC_VC);
     84 }
     85 
     86 
     87 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
     88 {
     89   switch(CC) {
     90   case SPCC::ICC_A:    return SPCC::ICC_N;
     91   case SPCC::ICC_N:    return SPCC::ICC_A;
     92   case SPCC::ICC_NE:   return SPCC::ICC_E;
     93   case SPCC::ICC_E:    return SPCC::ICC_NE;
     94   case SPCC::ICC_G:    return SPCC::ICC_LE;
     95   case SPCC::ICC_LE:   return SPCC::ICC_G;
     96   case SPCC::ICC_GE:   return SPCC::ICC_L;
     97   case SPCC::ICC_L:    return SPCC::ICC_GE;
     98   case SPCC::ICC_GU:   return SPCC::ICC_LEU;
     99   case SPCC::ICC_LEU:  return SPCC::ICC_GU;
    100   case SPCC::ICC_CC:   return SPCC::ICC_CS;
    101   case SPCC::ICC_CS:   return SPCC::ICC_CC;
    102   case SPCC::ICC_POS:  return SPCC::ICC_NEG;
    103   case SPCC::ICC_NEG:  return SPCC::ICC_POS;
    104   case SPCC::ICC_VC:   return SPCC::ICC_VS;
    105   case SPCC::ICC_VS:   return SPCC::ICC_VC;
    106 
    107   case SPCC::FCC_A:    return SPCC::FCC_N;
    108   case SPCC::FCC_N:    return SPCC::FCC_A;
    109   case SPCC::FCC_U:    return SPCC::FCC_O;
    110   case SPCC::FCC_O:    return SPCC::FCC_U;
    111   case SPCC::FCC_G:    return SPCC::FCC_ULE;
    112   case SPCC::FCC_LE:   return SPCC::FCC_UG;
    113   case SPCC::FCC_UG:   return SPCC::FCC_LE;
    114   case SPCC::FCC_ULE:  return SPCC::FCC_G;
    115   case SPCC::FCC_L:    return SPCC::FCC_UGE;
    116   case SPCC::FCC_GE:   return SPCC::FCC_UL;
    117   case SPCC::FCC_UL:   return SPCC::FCC_GE;
    118   case SPCC::FCC_UGE:  return SPCC::FCC_L;
    119   case SPCC::FCC_LG:   return SPCC::FCC_UE;
    120   case SPCC::FCC_UE:   return SPCC::FCC_LG;
    121   case SPCC::FCC_NE:   return SPCC::FCC_E;
    122   case SPCC::FCC_E:    return SPCC::FCC_NE;
    123   }
    124   llvm_unreachable("Invalid cond code");
    125 }
    126 
    127 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
    128                                    MachineBasicBlock *&TBB,
    129                                    MachineBasicBlock *&FBB,
    130                                    SmallVectorImpl<MachineOperand> &Cond,
    131                                    bool AllowModify) const
    132 {
    133 
    134   MachineBasicBlock::iterator I = MBB.end();
    135   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
    136   while (I != MBB.begin()) {
    137     --I;
    138 
    139     if (I->isDebugValue())
    140       continue;
    141 
    142     // When we see a non-terminator, we are done.
    143     if (!isUnpredicatedTerminator(I))
    144       break;
    145 
    146     // Terminator is not a branch.
    147     if (!I->isBranch())
    148       return true;
    149 
    150     // Handle Unconditional branches.
    151     if (I->getOpcode() == SP::BA) {
    152       UnCondBrIter = I;
    153 
    154       if (!AllowModify) {
    155         TBB = I->getOperand(0).getMBB();
    156         continue;
    157       }
    158 
    159       while (std::next(I) != MBB.end())
    160         std::next(I)->eraseFromParent();
    161 
    162       Cond.clear();
    163       FBB = nullptr;
    164 
    165       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
    166         TBB = nullptr;
    167         I->eraseFromParent();
    168         I = MBB.end();
    169         UnCondBrIter = MBB.end();
    170         continue;
    171       }
    172 
    173       TBB = I->getOperand(0).getMBB();
    174       continue;
    175     }
    176 
    177     unsigned Opcode = I->getOpcode();
    178     if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
    179       return true; // Unknown Opcode.
    180 
    181     SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
    182 
    183     if (Cond.empty()) {
    184       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
    185       if (AllowModify && UnCondBrIter != MBB.end() &&
    186           MBB.isLayoutSuccessor(TargetBB)) {
    187 
    188         // Transform the code
    189         //
    190         //    brCC L1
    191         //    ba L2
    192         // L1:
    193         //    ..
    194         // L2:
    195         //
    196         // into
    197         //
    198         //   brnCC L2
    199         // L1:
    200         //   ...
    201         // L2:
    202         //
    203         BranchCode = GetOppositeBranchCondition(BranchCode);
    204         MachineBasicBlock::iterator OldInst = I;
    205         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
    206           .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
    207         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
    208           .addMBB(TargetBB);
    209 
    210         OldInst->eraseFromParent();
    211         UnCondBrIter->eraseFromParent();
    212 
    213         UnCondBrIter = MBB.end();
    214         I = MBB.end();
    215         continue;
    216       }
    217       FBB = TBB;
    218       TBB = I->getOperand(0).getMBB();
    219       Cond.push_back(MachineOperand::CreateImm(BranchCode));
    220       continue;
    221     }
    222     // FIXME: Handle subsequent conditional branches.
    223     // For now, we can't handle multiple conditional branches.
    224     return true;
    225   }
    226   return false;
    227 }
    228 
    229 unsigned
    230 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
    231                              MachineBasicBlock *FBB,
    232                              ArrayRef<MachineOperand> Cond,
    233                              DebugLoc DL) const {
    234   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    235   assert((Cond.size() == 1 || Cond.size() == 0) &&
    236          "Sparc branch conditions should have one component!");
    237 
    238   if (Cond.empty()) {
    239     assert(!FBB && "Unconditional branch with multiple successors!");
    240     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
    241     return 1;
    242   }
    243 
    244   // Conditional branch
    245   unsigned CC = Cond[0].getImm();
    246 
    247   if (IsIntegerCC(CC))
    248     BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
    249   else
    250     BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
    251   if (!FBB)
    252     return 1;
    253 
    254   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
    255   return 2;
    256 }
    257 
    258 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
    259 {
    260   MachineBasicBlock::iterator I = MBB.end();
    261   unsigned Count = 0;
    262   while (I != MBB.begin()) {
    263     --I;
    264 
    265     if (I->isDebugValue())
    266       continue;
    267 
    268     if (I->getOpcode() != SP::BA
    269         && I->getOpcode() != SP::BCOND
    270         && I->getOpcode() != SP::FBCOND)
    271       break; // Not a branch
    272 
    273     I->eraseFromParent();
    274     I = MBB.end();
    275     ++Count;
    276   }
    277   return Count;
    278 }
    279 
    280 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
    281                                  MachineBasicBlock::iterator I, DebugLoc DL,
    282                                  unsigned DestReg, unsigned SrcReg,
    283                                  bool KillSrc) const {
    284   unsigned numSubRegs = 0;
    285   unsigned movOpc     = 0;
    286   const unsigned *subRegIdx = nullptr;
    287   bool ExtraG0 = false;
    288 
    289   const unsigned DW_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
    290   const unsigned DFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
    291   const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
    292   const unsigned QFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd,
    293                                           SP::sub_odd64_then_sub_even,
    294                                           SP::sub_odd64_then_sub_odd };
    295 
    296   if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
    297     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
    298       .addReg(SrcReg, getKillRegState(KillSrc));
    299   else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
    300     subRegIdx  = DW_SubRegsIdx;
    301     numSubRegs = 2;
    302     movOpc     = SP::ORrr;
    303     ExtraG0 = true;
    304   } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
    305     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
    306       .addReg(SrcReg, getKillRegState(KillSrc));
    307   else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
    308     if (Subtarget.isV9()) {
    309       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
    310         .addReg(SrcReg, getKillRegState(KillSrc));
    311     } else {
    312       // Use two FMOVS instructions.
    313       subRegIdx  = DFP_FP_SubRegsIdx;
    314       numSubRegs = 2;
    315       movOpc     = SP::FMOVS;
    316     }
    317   } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
    318     if (Subtarget.isV9()) {
    319       if (Subtarget.hasHardQuad()) {
    320         BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
    321           .addReg(SrcReg, getKillRegState(KillSrc));
    322       } else {
    323         // Use two FMOVD instructions.
    324         subRegIdx  = QFP_DFP_SubRegsIdx;
    325         numSubRegs = 2;
    326         movOpc     = SP::FMOVD;
    327       }
    328     } else {
    329       // Use four FMOVS instructions.
    330       subRegIdx  = QFP_FP_SubRegsIdx;
    331       numSubRegs = 4;
    332       movOpc     = SP::FMOVS;
    333     }
    334   } else if (SP::ASRRegsRegClass.contains(DestReg) &&
    335              SP::IntRegsRegClass.contains(SrcReg)) {
    336     BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
    337         .addReg(SP::G0)
    338         .addReg(SrcReg, getKillRegState(KillSrc));
    339   } else if (SP::IntRegsRegClass.contains(DestReg) &&
    340              SP::ASRRegsRegClass.contains(SrcReg)) {
    341     BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
    342         .addReg(SrcReg, getKillRegState(KillSrc));
    343   } else
    344     llvm_unreachable("Impossible reg-to-reg copy");
    345 
    346   if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
    347     return;
    348 
    349   const TargetRegisterInfo *TRI = &getRegisterInfo();
    350   MachineInstr *MovMI = nullptr;
    351 
    352   for (unsigned i = 0; i != numSubRegs; ++i) {
    353     unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
    354     unsigned Src = TRI->getSubReg(SrcReg,  subRegIdx[i]);
    355     assert(Dst && Src && "Bad sub-register");
    356 
    357     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
    358     if (ExtraG0)
    359       MIB.addReg(SP::G0);
    360     MIB.addReg(Src);
    361     MovMI = MIB.getInstr();
    362   }
    363   // Add implicit super-register defs and kills to the last MovMI.
    364   MovMI->addRegisterDefined(DestReg, TRI);
    365   if (KillSrc)
    366     MovMI->addRegisterKilled(SrcReg, TRI);
    367 }
    368 
    369 void SparcInstrInfo::
    370 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    371                     unsigned SrcReg, bool isKill, int FI,
    372                     const TargetRegisterClass *RC,
    373                     const TargetRegisterInfo *TRI) const {
    374   DebugLoc DL;
    375   if (I != MBB.end()) DL = I->getDebugLoc();
    376 
    377   MachineFunction *MF = MBB.getParent();
    378   const MachineFrameInfo &MFI = *MF->getFrameInfo();
    379   MachineMemOperand *MMO = MF->getMachineMemOperand(
    380       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
    381       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
    382 
    383   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
    384   if (RC == &SP::I64RegsRegClass)
    385     BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
    386       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
    387   else if (RC == &SP::IntRegsRegClass)
    388     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
    389       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
    390   else if (RC == &SP::IntPairRegClass)
    391     BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
    392       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
    393   else if (RC == &SP::FPRegsRegClass)
    394     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
    395       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
    396   else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
    397     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
    398       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
    399   else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
    400     // Use STQFri irrespective of its legality. If STQ is not legal, it will be
    401     // lowered into two STDs in eliminateFrameIndex.
    402     BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
    403       .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
    404   else
    405     llvm_unreachable("Can't store this register to stack slot");
    406 }
    407 
    408 void SparcInstrInfo::
    409 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    410                      unsigned DestReg, int FI,
    411                      const TargetRegisterClass *RC,
    412                      const TargetRegisterInfo *TRI) const {
    413   DebugLoc DL;
    414   if (I != MBB.end()) DL = I->getDebugLoc();
    415 
    416   MachineFunction *MF = MBB.getParent();
    417   const MachineFrameInfo &MFI = *MF->getFrameInfo();
    418   MachineMemOperand *MMO = MF->getMachineMemOperand(
    419       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
    420       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
    421 
    422   if (RC == &SP::I64RegsRegClass)
    423     BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
    424       .addMemOperand(MMO);
    425   else if (RC == &SP::IntRegsRegClass)
    426     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
    427       .addMemOperand(MMO);
    428   else if (RC == &SP::IntPairRegClass)
    429     BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
    430       .addMemOperand(MMO);
    431   else if (RC == &SP::FPRegsRegClass)
    432     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
    433       .addMemOperand(MMO);
    434   else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
    435     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
    436       .addMemOperand(MMO);
    437   else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
    438     // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
    439     // lowered into two LDDs in eliminateFrameIndex.
    440     BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
    441       .addMemOperand(MMO);
    442   else
    443     llvm_unreachable("Can't load this register from stack slot");
    444 }
    445 
    446 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
    447 {
    448   SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
    449   unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
    450   if (GlobalBaseReg != 0)
    451     return GlobalBaseReg;
    452 
    453   // Insert the set of GlobalBaseReg into the first MBB of the function
    454   MachineBasicBlock &FirstMBB = MF->front();
    455   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
    456   MachineRegisterInfo &RegInfo = MF->getRegInfo();
    457 
    458   const TargetRegisterClass *PtrRC =
    459     Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
    460   GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
    461 
    462   DebugLoc dl;
    463 
    464   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
    465   SparcFI->setGlobalBaseReg(GlobalBaseReg);
    466   return GlobalBaseReg;
    467 }
    468