| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 104 unsigned SrcReg = MI->getOperand(i).getReg();
105 if (SrcReg == DstReg)
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
125 SingleValReg = SrcReg;
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| RegisterCoalescer.h | 36 unsigned SrcReg;
41 /// The sub-register index of the old SrcReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
103 unsigned getSrcReg() const { return SrcReg; }
108 /// Return the subregister index that SrcReg will be coalesced into, or 0.
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| MachineSSAUpdater.cpp | 96 unsigned SrcReg = I->getOperand(i).getReg();
98 if (AVals[SrcBB] != SrcReg) {
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| MachineSink.cpp | 162 unsigned SrcReg = MI->getOperand(1).getReg();
164 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
166 !MRI->hasOneNonDBGUse(SrcReg))
169 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
179 MRI->replaceRegWith(DstReg, SrcReg);
184 MRI->clearKillFlags(SrcReg);
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| MachineCSE.cpp | 136 unsigned SrcReg = DefMI->getOperand(1).getReg();
137 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
145 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
147 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
156 if (!MRI->constrainRegClass(SrcReg, RC))
160 // Propagate SrcReg of copies to MI.
161 MO.setReg(SrcReg);
162 MRI->clearKillFlags(SrcReg);
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| PHIElimination.cpp | 361 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
364 isImplicitlyDefined(SrcReg, MRI);
365 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
381 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
401 .addReg(SrcReg, 0, SrcSubReg);
405 // We only need to update the LiveVariables kill of SrcReg if this was the
406 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
409 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
410 !LV->isLiveOut(SrcReg, opBlock))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 243 // STriw_pred [R30], ofst, SrcReg;
249 int SrcReg = MI->getOperand(2).getReg();
250 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
261 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
270 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
279 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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| HexagonPeephole.cpp | 142 unsigned SrcReg = Src.getReg();
145 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
149 PeepholeMap[DstReg] = SrcReg;
164 unsigned SrcReg = Src2.getReg();
165 PeepholeMap[DstReg] = SrcReg;
181 unsigned SrcReg = Src1.getReg();
183 std::make_pair(*&SrcReg, Hexagon::subreg_hireg);
193 unsigned SrcReg = Src.getReg();
196 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
200 PeepholeMap[DstReg] = SrcReg;
[all...] |
| HexagonCopyToCombine.cpp | 125 unsigned SrcReg = Op1.getReg();
127 Hexagon::IntRegsRegClass.contains(SrcReg);
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 186 unsigned SrcReg = MI.getOperand(2).getReg();
187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
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| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 133 unsigned SrcReg = Copy.getOperand(1).getReg();
136 TargetRegisterInfo::isVirtualRegister(SrcReg) ?
137 MRI.getRegClass(SrcReg) :
138 TRI.getPhysRegClass(SrcReg);
217 unsigned SrcReg = MI.getOperand(I).getReg();
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
193 SrcReg = MCI.getOperand(1).getReg();
197 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
198 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
202 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
211 SrcReg = MCI.getOperand(1).getReg();
213 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
232 SrcReg = MCI.getOperand(1).getReg();
234 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
242 SrcReg = MCI.getOperand(1).getReg()
[all...] |
| HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
115 SrcReg = MI.getOperand(1).getReg();
117 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
127 SrcReg = MI.getOperand(1).getReg();
129 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg))
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| /external/mesa3d/src/mesa/main/ |
| atifragshader.h | 55 struct atifragshader_src_register SrcReg[2][3];
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 158 unsigned SrcReg = DefMI->getOperand(i).getReg();
159 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
160 DefMI = MRI->getVRegDef(SrcReg);
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| Thumb2ITBlockPass.cpp | 133 unsigned SrcReg = MI->getOperand(1).getReg();
136 if (Uses.count(DstReg) || Defs.count(SrcReg))
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| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 134 unsigned SrcReg = I->getOperand(0).getReg();
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
137 .addReg(SrcReg);
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| MipsSEInstrInfo.cpp | 81 unsigned DestReg, unsigned SrcReg,
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 } else if (Mips::CCRRegClass.contains(SrcReg))
94 else if (Mips::FGR32RegClass.contains(SrcReg))
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
98 SrcReg = 0;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
101 SrcReg = 0;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 201 unsigned SrcReg = getCompareSourceReg(Compare);
204 if (getRegReferences(MBBI, SrcReg))
341 unsigned SrcReg = getCompareSourceReg(Compare);
349 if (resultTests(MI, SrcReg)) {
364 SrcRefs |= getRegReferences(MI, SrcReg);
393 unsigned SrcReg = Compare->getOperand(0).getReg();
398 if (MBBI->modifiesRegister(SrcReg, TRI) ||
425 // Clear any intervening kills of SrcReg and SrcReg2.
428 MBBI->clearRegisterKills(SrcReg, TRI);
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| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 245 unsigned SrcReg = LEA->getOperand(1 + X86::AddrBaseReg).getReg();
248 return SrcReg == DstReg &&
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
[all...] |
| radeon_program.h | 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 442 unsigned SrcReg = ValueMap[V];
443 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
447 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
479 unsigned SrcReg = ValueMap[V];
480 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
484 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 465 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
478 unsigned SrcReg = MI.getOperand(0).getReg();
481 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
483 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
487 if (SrcReg != PPC::CR0) {
494 .addImm(getEncodingValue(SrcReg) * 4)
553 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
566 unsigned SrcReg = MI.getOperand(0).getReg();
569 getCRFromCRBit(SrcReg))
570 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()))
[all...] |
| /external/mesa3d/src/mesa/program/ |
| program_parser.h | 127 struct asm_src_register SrcReg[3];
|
