| /external/llvm/lib/CodeGen/ |
| AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
103 bool IsStore, IsLoad;
109 IsLoad = true;
114 IsLoad = false;
119 IsStore = IsLoad = true;
130 IsStore = IsLoad = true;
134 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad);
179 bool IsStore, bool IsLoad) {
182 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad);
184 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad);
[all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 215 bool IsLoad = TII->get(LoadStoreOp).mayLoad();
244 .addReg(SubReg, getDefRegState(IsLoad))
251 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad))
|
| /external/v8/src/arm64/ |
| instructions-arm64.cc | 16 bool Instruction::IsLoad() const {
|
| /external/clang/include/clang/StaticAnalyzer/Core/ |
| Checker.h | 197 const SVal &location, bool isLoad, const Stmt *S,
199 ((const CHECKER *)checker)->checkLocation(location, isLoad, S, C);
529 bool IsLoad;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 78 unsigned int IsLoad : 1;
342 SwapVector[VecIdx].IsLoad = 1;
348 SwapVector[VecIdx].IsLoad = 1;
357 SwapVector[VecIdx].IsLoad = 1;
663 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
697 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
728 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
[all...] |
| /external/v8/test/unittests/compiler/ |
| interpreter-assembler-unittest.cc | 69 Matcher<Node*> InterpreterAssemblerTest::InterpreterAssemblerForTest::IsLoad(
72 return ::i::compiler::IsLoad(rep_matcher, base_matcher, index_matcher, _, _);
88 return IsLoad(
98 Matcher<Node*> load_matcher = IsLoad(
114 return IsLoad(
120 Matcher<Node*> first_byte = IsLoad(
125 Matcher<Node*> second_byte = IsLoad(
147 load_matcher = IsLoad(
163 Matcher<Node*> hi_byte = IsLoad(
169 Matcher<Node*> lo_byte = IsLoad(
[all...] |
| node-test-utils.cc | [all...] |
| /external/vixl/src/vixl/a64/ |
| instructions-a64.cc | 74 bool Instruction::IsLoad() const {
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| CheckerManager.cpp | 293 bool IsLoad;
302 SVal loc, bool isLoad, const Stmt *NodeEx,
305 : Checkers(checkers), Loc(loc), IsLoad(isLoad), NodeEx(NodeEx),
310 ProgramPoint::Kind K = IsLoad ? ProgramPoint::PreLoadKind :
317 checkFn(Loc, IsLoad, BoundEx, C);
326 SVal location, bool isLoad,
330 CheckLocationContext C(LocationCheckers, location, isLoad, NodeEx,
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 107 bool IsLoad;
382 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
447 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
523 if (TableEntry->IsLoad) {
548 if (!TableEntry->IsLoad)
573 if (TableEntry->IsLoad)
[all...] |
| ARMLoadStoreOptimizer.cpp | 454 bool IsLoad =
459 if (IsLoad || IsStore) {
777 bool IsLoad = isi32Load(Opcode);
778 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
779 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8;
784 if (IsLoad) {
799 bool IsLoad = isLoadSingle(Opcode);
814 if (IsLoad) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 853 bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore();
854 if (!IsLoad && !IsStore)
[all...] |
| /external/clang/lib/CodeGen/ |
| CGAtomic.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/v8/src/crankshaft/ |
| hydrogen.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
