| /external/clang/test/CodeGenCXX/ |
| 2010-03-09-AnonAggregate.cpp | 6 class MO {
12 class MO m;
|
| /external/llvm/lib/Target/BPF/ |
| BPFMCInstLower.cpp | 29 BPFMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
30 return Printer.getSymbol(MO.getGlobal());
33 MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
38 if (!MO.isJTI() && MO.getOffset())
48 const MachineOperand &MO = MI->getOperand(i);
51 switch (MO.getType()) {
57 if (MO.isImplicit())
59 MCOp = MCOperand::createReg(MO.getReg());
62 MCOp = MCOperand::createImm(MO.getImm())
[all...] |
| BPFAsmPrinter.cpp | 51 const MachineOperand &MO = MI->getOperand(OpNum);
53 switch (MO.getType()) {
55 O << BPFInstPrinter::getRegisterName(MO.getReg());
59 O << MO.getImm();
63 O << *MO.getMBB()->getSymbol();
67 O << *getSymbol(MO.getGlobal());
|
| /external/llvm/lib/Target/Sparc/ |
| SparcMCInstLower.cpp | 32 const MachineOperand &MO,
36 (SparcMCExpr::VariantKind)MO.getTargetFlags();
39 switch(MO.getType()) {
42 Symbol = MO.getMBB()->getSymbol();
46 Symbol = AP.getSymbol(MO.getGlobal());
50 Symbol = AP.GetBlockAddressSymbol(MO.getBlockAddress());
54 Symbol = AP.GetExternalSymbolSymbol(MO.getSymbolName());
58 Symbol = AP.GetCPISymbol(MO.getIndex());
70 const MachineOperand &MO,
72 switch(MO.getType())
[all...] |
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 73 const MachineOperand &MO = MI->getOperand(i);
74 if (MO.isReg() && MO.isDef()) {
75 unsigned Reg = MO.getReg();
139 const MachineOperand &MO = MI->getOperand(i);
140 if (MO.isReg() && MO.isDef()) {
141 unsigned Reg = MO.getReg();
150 } else if (MO.isRegMask()) {
152 LivePhysRegs.clearBitsNotInMask(MO.getRegMask())
[all...] |
| StackMapLivenessAnalysis.cpp | 150 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask);
151 MI.addOperand(MF, MO);
|
| ExpandPostRAPseudos.cpp | 73 MachineOperand &MO = MI->getOperand(i);
74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
76 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 66 for (const MachineOperand &MO : MI.implicit_operands())
67 if (MO.isReg() && MO.isDef())
68 if (TRI->regsOverlap(Reg, MO.getReg()))
92 MachineOperand &MO = MI.getOperand(i);
93 if (MO.isReg() && MO.isDead() && MO.isDef()) {
94 assert(!MO.isImplicit() && "Unexpected implicit def!");
104 if (implicitlyDefinesOverlappingReg(MO.getReg(), MI))
[all...] |
| AArch64ExpandPseudoInsts.cpp | 66 const MachineOperand &MO = OldMI.getOperand(i);
67 assert(MO.isReg() && MO.getReg());
68 if (MO.isUse())
69 UseMI.addOperand(MO);
71 DefMI.addOperand(MO);
|
| /external/llvm/lib/Target/ARM/ |
| ARMMCInstLower.cpp | 27 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
30 unsigned Option = MO.getTargetFlags() & ARMII::MO_OPTION_MASK;
59 if (!MO.isJTI() && MO.getOffset())
61 MCConstantExpr::create(MO.getOffset(),
68 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
70 switch (MO.getType()) {
74 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
76 assert(!MO.getSubReg() && "Subregs should be eliminated!")
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 34 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
42 switch (MO.getTargetFlags()) {
65 if (!MO.isJTI() && MO.getOffset())
66 ME = MCBinaryExpr::createAdd(ME, MCConstantExpr::create(MO.getOffset(), MC),
90 const MachineOperand &MO = MI->getOperand(i);
92 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
95 switch (MO.getType()) {
101 if (MO.isImplicit()) continue;
102 MCO = MCOperand::createReg(MO.getReg())
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 66 const MachineOperand &MO = MI->getOperand(OpNum);
67 switch (MO.getType()) {
70 O << MSP430InstPrinter::getRegisterName(MO.getReg());
75 O << MO.getImm();
78 MO.getMBB()->getSymbol()->print(O, MAI);
82 uint64_t Offset = MO.getOffset();
95 getSymbol(MO.getGlobal())->print(O, MAI);
|
| MSP430MCInstLower.cpp | 32 GetGlobalAddressSymbol(const MachineOperand &MO) const {
33 switch (MO.getTargetFlags()) {
38 return Printer.getSymbol(MO.getGlobal());
42 GetExternalSymbolSymbol(const MachineOperand &MO) const {
43 switch (MO.getTargetFlags()) {
48 return Printer.GetExternalSymbolSymbol(MO.getSymbolName());
52 GetJumpTableSymbol(const MachineOperand &MO) const {
57 << MO.getIndex();
59 switch (MO.getTargetFlags()) {
69 GetConstantPoolIndexSymbol(const MachineOperand &MO) const
[all...] |
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 110 const MCOperand &MO = MI->getOperand (opNum);
112 if (MO.isReg()) {
113 printRegName(O, MO.getReg());
117 if (MO.isImm()) {
118 O << (int)MO.getImm();
122 assert(MO.isExpr() && "Unknown operand kind in printOperand");
123 MO.getExpr()->print(O, &MAI);
137 const MCOperand &MO = MI->getOperand(opNum+1);
139 if (MO.isReg() && MO.getReg() == SP::G0
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMCInstLower.cpp | 37 SystemZMCInstLower::getExpr(const MachineOperand &MO,
41 switch (MO.getType()) {
43 Symbol = MO.getMBB()->getSymbol();
48 Symbol = AsmPrinter.getSymbol(MO.getGlobal());
52 Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
56 Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
61 Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
65 Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
73 if (int64_t Offset = MO.getOffset()) {
80 MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMCInstLower.cpp | 31 WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
32 return Printer.getSymbol(MO.getGlobal());
36 const MachineOperand &MO) const {
37 return Printer.GetExternalSymbolSymbol(MO.getSymbolName());
40 MCOperand WebAssemblyMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
42 assert(MO.getTargetFlags() == 0 && "WebAssembly does not use target flags");
46 int64_t Offset = MO.getOffset();
48 assert(!MO.isJTI() && "Unexpected offset with jump table index");
61 const MachineOperand &MO = MI->getOperand(i);
64 switch (MO.getType())
[all...] |
| WebAssemblyPeephole.cpp | 70 MachineOperand &MO = MI.getOperand(0);
71 unsigned OldReg = MO.getReg();
77 MO.setReg(NewReg);
78 MO.setIsDead();
|
| /external/llvm/lib/Target/XCore/ |
| XCoreMCInstLower.cpp | 35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
43 Symbol = MO.getMBB()->getSymbol();
46 Symbol = Printer.getSymbol(MO.getGlobal());
47 Offset += MO.getOffset();
50 Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress());
51 Offset += MO.getOffset();
54 Symbol = Printer.GetExternalSymbolSymbol(MO.getSymbolName());
55 Offset += MO.getOffset();
58 Symbol = Printer.GetJTISymbol(MO.getIndex());
61 Symbol = Printer.GetCPISymbol(MO.getIndex())
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 34 const MachineOperand &MO = MI->getOperand(i);
37 switch (MO.getType()) {
41 const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
48 MCOp = MCOperand::CreateImm(MO.getImm());
51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| AMDGPUAsmPrinter.cpp | 70 MachineOperand & MO = MI.getOperand(op_idx);
76 if (!MO.isReg()) {
79 reg = MO.getReg();
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mmix-opc.c | 84 #define MO mmix_type_memaccess_octa
212 {"ldo", Z (0x8c), OP (regs_z_opt), MO},
215 {"ldou", Z (0x8e), OP (regs_z_opt), MO},
227 {"cswap", Z (0x94), OP (regs_z_opt), MO},
230 {"ldunc", Z (0x96), OP (regs_z_opt), MO},
241 {"sto", Z (0xac), OP (regs_z_opt), MO},
244 {"stou", Z (0xae), OP (regs_z_opt), MO},
252 {"stco", Z (0xb4), OP (x_regs_z), MO},
255 {"stunc", Z (0xb6), OP (regs_z_opt), MO},
|
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 94 const MCOperand &MO = MI->getOperand(OpNum);
95 int64_t Imm = MO.getImm();
144 const MCOperand &MO = MI->getOperand(OpNum);
145 int64_t Imm = MO.getImm();
218 const MCOperand &MO = MI->getOperand(OpNum);
219 int Imm = (int) MO.getImm();
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 218 MachineOperand &MO = MI->getOperand(i);
219 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
220 MO.setIsKill(false);
254 MachineOperand &MO = MI->getOperand(i);
255 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
256 MO.setIsDead(false)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 44 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
163 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
165 if (MO.isExpr())
168 assert(!MO.isFPImm());
170 if (!MO.isImm())
174 return getLit32Encoding(static_cast<uint32_t>(MO.getImm()));
178 return getLit64Encoding(static_cast<uint64_t>(MO.getImm()));
231 const MCOperand &MO = MI.getOperand(OpNo);
233 if (MO.isExpr())
[all...] |
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 49 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
76 const MCOperand &MO,
79 if (MO.isReg())
80 return MRI.getEncodingValue(MO.getReg());
81 if (MO.isImm())
82 return static_cast<unsigned>(MO.getImm());
84 assert(MO.isExpr());
86 const MCExpr *Expr = MO.getExpr();
127 const MCOperand &MO = MI.getOperand(1);
128 uint64_t Imm = MO.isImm() ? MO.getImm() : 0
[all...] |
