| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| ArithOpChanger.java | 25 import dexfuzz.rawdex.Opcode;
144 stats.incrementStat("Changed arithmetic opcode");
151 Opcode opcode = mInsn.insn.info.opcode; local
152 if (Opcode.isBetween(opcode, Opcode.ADD_INT, Opcode.USHR_INT_LIT8)) {
158 private Opcode getLegalDifferentOpcode(MInsn mInsn)
159 Opcode opcode = mInsn.insn.info.opcode; local
[all...] |
| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/builder/ |
| PayloadAlignmentTest.java | 35 import org.jf.dexlib2.Opcode;
53 implBuilder.addInstruction(new BuilderInstruction10x(Opcode.NOP));
63 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
70 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
79 Assert.assertEquals(instruction.getOpcode(), Opcode.MOVE);
82 Assert.assertEquals(instruction.getOpcode(), Opcode.NOP);
85 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
93 implBuilder.addInstruction(new BuilderInstruction31t(Opcode.FILL_ARRAY_DATA, 0, label));
94 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
95 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| ThumbRegisterInfo.cpp | 338 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
340 static unsigned convertToNonSPOpcode(unsigned Opcode) {
341 switch (Opcode) {
349 return Opcode;
362 unsigned Opcode = MI.getOpcode();
366 if (Opcode == ARM::tADDframe) {
398 unsigned NewOpc = convertToNonSPOpcode(Opcode);
399 if (NewOpc != Opcode && FrameReg != ARM::SP)
410 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 86 int Opcode = InstIn.getOpcode();
88 if (Opcode == Mips::DEXT)
105 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
178 unsigned Opcode = TmpInst.getOpcode();
179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
180 (Opcode != Mips::SLL_MM) && !Binary)
181 llvm_unreachable("unimplemented opcode in encodeInstruction()");
186 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6)
[all...] |
| MipsNaClELFStreamer.cpp | 66 unsigned Opcode = MI.getOpcode();
70 switch (Opcode) {
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
207 switch (Opcode) {
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 119 unsigned Opcode = Node->getOpcode();
131 switch (Opcode) {
|
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 24 enum Opcode {
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 71 unsigned Opcode = MI->getOpcode();
73 switch (Opcode) {
107 if (Opcode == ARM::t2HINT)
169 if (Opcode == ARM::t2STMDB_UPD)
198 if (Opcode == ARM::t2LDMIA_UPD)
278 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
283 NewMI.setOpcode(Opcode);
804 unsigned Opcode = MI->getOpcode();
807 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP])
[all...] |
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 110 unsigned Opcode = MI.getOpcode();
114 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 88 unsigned Opcode;
90 Opcode = Hexagon::S2_storerd_pci;
92 Opcode = Hexagon::S2_storeri_pci;
94 Opcode = Hexagon::S2_storerh_pci;
96 Opcode = Hexagon::S2_storerf_pci;
98 Opcode = Hexagon::S2_storerb_pci;
111 TII->get(Opcode));
128 unsigned Opcode;
130 Opcode = Hexagon::L2_loadrd_pci;
132 Opcode = Hexagon::L2_loadri_pci
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 85 unsigned Opcode = MI->getOpcode();
86 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
96 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode;
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/ |
| Opcode.java | 42 public enum Opcode
44 NOP(0x00, "nop", ReferenceType.NONE, Format.Format10x, Opcode.CAN_CONTINUE),
45 MOVE(0x01, "move", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
46 MOVE_FROM16(0x02, "move/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
47 MOVE_16(0x03, "move/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER),
48 MOVE_WIDE(0x04, "move-wide", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER | Opcode.SETS_WIDE_REGISTER)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600EmitClauseMarkers.cpp | 274 unsigned Opcode = PushBeforeModifier ?
276 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
|
| R600ExpandSpecialInstrs.cpp | 103 // The native opcode used by PRED_X is stored as an immediate in the
106 MI.getOperand(2).getImm(), // opcode
219 unsigned Opcode = BMI->getOpcode();
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
315 unsigned Opcode = MI.getOpcode();
316 switch (Opcode) {
318 Opcode = AMDGPU::CUBE_r600_real;
321 Opcode = AMDGPU::CUBE_eg_real;
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1)
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 583 unsigned Opcode = MIb.getOpcode();
584 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
591 // ordered such that the numerically smaller opcode is in slot 1.
695 // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 186 unsigned Opcode = Node->getOpcode();
204 switch(Opcode) {
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 311 unsigned Opcode = C->getOpcode();
312 switch (Opcode) {
355 if (Instruction::isBinaryOp(Opcode)) {
360 if (Instruction::isCast(Opcode)) {
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 108 unsigned Opcode = MI.getOpcode();
109 const MCInstrDesc &Desc = MCII.get(Opcode);
110 if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 278 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
333 unsigned Opcode = MI->getOpcode();
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
370 if (HasCTRSet && Opcode == PPC::BCTRL)
391 unsigned Opcode = MI->getOpcode();
394 GetInstrType(Opcode, isFirst, isSingle, isCracked,
399 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
|
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 68 unsigned Opcode = MI.getOpcode();
70 switch (Opcode) {
79 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
95 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {
96 unsigned Op = (Opcode == X86::TCRETURNdi)
108 } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
109 unsigned Op = (Opcode == X86::TCRETURNmi
[all...] |
| X86OptimizeLEAs.cpp | 187 unsigned Opcode = MI.getOpcode();
188 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
189 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
241 unsigned Opcode = MI.getOpcode();
249 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, Opcode);
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 36 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
