| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
388 Reg1 = getXRegFromWReg(Reg1);
391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
407 Reg1 = getDRegFromBReg(Reg1);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 227 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
251 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
266 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 488 unsigned Reg1 = Reg;
493 .addReg(Reg1, RegState::Kill)
533 unsigned Reg1 = Reg;
539 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
577 unsigned Reg1 = Reg;
582 .addReg(Reg1, RegState::Kill)
[all...] |
| PPCVSXSwapRemoval.cpp | 837 unsigned Reg1 = MI->getOperand(1).getReg();
840 MI->getOperand(2).setReg(Reg1);
[all...] |
| PPCInstrInfo.cpp | 349 unsigned Reg1 = MI->getOperand(1).getReg();
358 if (Reg0 == Reg1) {
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
392 MI->getOperand(2).setReg(Reg1);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
600 uint16_t Reg1;
602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
606 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
622 Reg0 = Reg1;
623 Reg1 = 0;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 738 unsigned Reg1 = CSI[idx].getReg();
760 if (AArch64::GPR64RegClass.contains(Reg1)) {
768 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 659 unsigned Reg1 = MI->getOperand(1).getReg();
664 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
670 if (Reg1 != Reg0)
677 } else if (Reg0 != Reg1) {
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMFastISel.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 442 unsigned Reg1 =
446 std::swap(Reg0, Reg1);
454 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
459 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
462 std::swap(Reg0, Reg1);
470 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 140 unsigned Reg1 = MI->getOperand(Idx1).getReg();
153 if (HasDef && Reg0 == Reg1 &&
161 Reg0 = Reg1;
175 MI->getOperand(Idx2).setReg(Reg1);
[all...] |
| RegisterCoalescer.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
