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Searched
defs:Registers
(Results
1 - 14
of
14
) sorted by null
/external/mesa3d/src/mesa/swrast/
s_atifragshader.c
36
GLfloat
Registers
[6][4]; /** six temporary
registers
*/
236
COPY_4V(machine->PrevPassRegisters[i], machine->
Registers
[i]);
265
COPY_4V(machine->
Registers
[idx],
270
COPY_4V(machine->
Registers
[idx], machine->PrevPassRegisters[pass_tex]);
272
apply_swizzle(machine->
Registers
[idx], swizzle);
296
fetch_texel(ctx, tex_coords, 0.0F, idx, machine->
Registers
[idx]);
346
/* setup the source
registers
for color and alpha ops */
353
machine->
Registers
[index - GL_REG_0_ATI]);
536
/* write out the destination
registers
*/
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all
...]
/external/autotest/client/cros/
power_utils.py
502
class
Registers
(object):
503
"""Class to examine PCI and MSR
registers
."""
/external/v8/src/mips/
constants-mips.h
126
//
Registers
and FPURegisters.
128
// Number of general purpose
registers
.
132
// Number of
registers
with HI, LO, and pc.
138
// Number coprocessor
registers
.
142
// FPU (coprocessor 1) control
registers
. Currently only FCSR is implemented.
187
class
Registers
{
243
// the simulator will run through them and print the
registers
.
601
SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR
registers
.
603
SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR
registers
.
817
//
registers
and other constants
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/external/v8/src/mips64/
constants-mips64.h
102
//
Registers
and FPURegisters.
104
// Number of general purpose
registers
.
108
// Number of
registers
with HI, LO, and pc.
114
// Number coprocessor
registers
.
118
// FPU (coprocessor 1) control
registers
. Currently only FCSR is implemented.
163
class
Registers
{
219
// the simulator will run through them and print the
registers
.
642
MOVZ_C = ((2U << 3) + 2), // COP1 on FPR
registers
.
643
MOVN_C = ((2U << 3) + 3), // COP1 on FPR
registers
.
644
SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR
registers
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...]
/external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp
38
// runEnums - Print out enum values for all of the
registers
.
70
// runEnums - Print out enum values for all of the
registers
.
73
const auto &
Registers
= Bank.getRegisters();
76
assert(
Registers
.size() <= 0xffff && "Too many regs to fit in tables");
79
Registers
.front().TheDef->getValueAsString("Namespace");
96
for (const auto &Reg :
Registers
)
98
assert(
Registers
.size() ==
Registers
.back().EnumValue &&
100
OS << " NUM_TARGET_REGS \t// " <<
Registers
.size()+1 << "\n";
248
<< "// This limit must be adjusted dynamically for reserved
registers
.\n
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...]
AsmWriterEmitter.cpp
530
const std::deque<CodeGenRegister> &
Registers
) {
532
SmallVector<std::string, 4> AsmNames(
Registers
.size());
534
for (const auto &Reg :
Registers
) {
574
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i) {
586
const auto &
Registers
= Target.getRegBank().getRegisters();
590
Registers
.front().TheDef->getValueAsString("Namespace");
601
O << " assert(RegNo && RegNo < " << (
Registers
.size()+1)
607
emitRegisterNameString(O, AltNameIndices[i]->getName(),
Registers
);
609
emitRegisterNameString(O, "",
Registers
);
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...]
CodeGenRegisters.h
66
// Are all super-
registers
containing this SubRegIndex covered by their
67
// sub-
registers
?
146
// Lazily compute a map of all sub-
registers
.
147
// This includes unique entries for all sub-sub-
registers
.
150
// Compute extra sub-
registers
by combining the existing sub-
registers
.
153
// Add this as a super-register to all sub-
registers
after the sub-register
158
assert(SubRegsComplete && "Must precompute sub-
registers
");
162
// Add sub-
registers
to OSet following a pre-order defined by the .td file.
174
// Get the list of super-
registers
in topological order, small to large
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...]
AsmMatcherEmitter.cpp
197
/// For register classes: the records for all the
registers
in this class.
198
RegisterSet
Registers
;
220
//
Registers
classes are only related to
registers
classes, and only if
228
std::set_intersection(
Registers
.begin(),
Registers
.end(),
229
RHS.
Registers
.begin(), RHS.
Registers
.end(),
855
// Collect singleton
registers
, if used.
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all
...]
CodeGenRegisters.cpp
130
// Also compute leading super-
registers
. Each register has a list of
131
// covered-by-subregs super-
registers
where it appears as the first explicit
139
//
registers
, so build a symmetric graph by adding links in both ends.
154
// Iterate over all register units in a set of
registers
.
230
// Map explicit sub-
registers
first, so the names take precedence.
231
// The inherited sub-
registers
are mapped below.
336
// sub-
registers
. By doing this before computeSecondarySubRegs(), we ensure
357
// sub-
registers
, the other
registers
won't contribute any more units.
378
//
registers
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...]
/external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp
[
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...]
/external/v8/src/arm/
constants-arm.h
39
// Number of
registers
in normal ARM mode.
671
class
Registers
{
/external/v8/src/ppc/
constants-ppc.h
17
// Number of
registers
456
// These constants are declared in assembler-arm.cc, as they use named
registers
578
class
Registers
{
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
143
// Map of register aliases
registers
via the .req directive.
425
SmallVector<unsigned, 8>
Registers
;
472
// A vector register list is a sequential list of 1 to 4
registers
.
606
return
Registers
;
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...]
/external/robolectric/v1/lib/main/
sqlite-jdbc-3.7.2.jar
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