1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is emits an assembly printer for the current target. 11 // Note that this is currently fairly skeletal, but will grow over time. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AsmWriterInst.h" 16 #include "CodeGenTarget.h" 17 #include "SequenceToOffsetTable.h" 18 #include "llvm/ADT/SmallString.h" 19 #include "llvm/ADT/StringExtras.h" 20 #include "llvm/ADT/Twine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/Format.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <map> 30 #include <vector> 31 using namespace llvm; 32 33 #define DEBUG_TYPE "asm-writer-emitter" 34 35 namespace { 36 class AsmWriterEmitter { 37 RecordKeeper &Records; 38 CodeGenTarget Target; 39 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap; 40 const std::vector<const CodeGenInstruction*> *NumberedInstructions; 41 std::vector<AsmWriterInst> Instructions; 42 std::vector<std::string> PrintMethods; 43 public: 44 AsmWriterEmitter(RecordKeeper &R); 45 46 void run(raw_ostream &o); 47 48 private: 49 void EmitPrintInstruction(raw_ostream &o); 50 void EmitGetRegisterName(raw_ostream &o); 51 void EmitPrintAliasInstruction(raw_ostream &O); 52 53 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { 54 assert(ID < NumberedInstructions->size()); 55 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I = 56 CGIAWIMap.find(NumberedInstructions->at(ID)); 57 assert(I != CGIAWIMap.end() && "Didn't find inst!"); 58 return I->second; 59 } 60 void FindUniqueOperandCommands(std::vector<std::string> &UOC, 61 std::vector<unsigned> &InstIdxs, 62 std::vector<unsigned> &InstOpsUsed) const; 63 }; 64 } // end anonymous namespace 65 66 static void PrintCases(std::vector<std::pair<std::string, 67 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) { 68 O << " case " << OpsToPrint.back().first << ": "; 69 AsmWriterOperand TheOp = OpsToPrint.back().second; 70 OpsToPrint.pop_back(); 71 72 // Check to see if any other operands are identical in this list, and if so, 73 // emit a case label for them. 74 for (unsigned i = OpsToPrint.size(); i != 0; --i) 75 if (OpsToPrint[i-1].second == TheOp) { 76 O << "\n case " << OpsToPrint[i-1].first << ": "; 77 OpsToPrint.erase(OpsToPrint.begin()+i-1); 78 } 79 80 // Finally, emit the code. 81 O << TheOp.getCode(); 82 O << "break;\n"; 83 } 84 85 86 /// EmitInstructions - Emit the last instruction in the vector and any other 87 /// instructions that are suitably similar to it. 88 static void EmitInstructions(std::vector<AsmWriterInst> &Insts, 89 raw_ostream &O) { 90 AsmWriterInst FirstInst = Insts.back(); 91 Insts.pop_back(); 92 93 std::vector<AsmWriterInst> SimilarInsts; 94 unsigned DifferingOperand = ~0; 95 for (unsigned i = Insts.size(); i != 0; --i) { 96 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 97 if (DiffOp != ~1U) { 98 if (DifferingOperand == ~0U) // First match! 99 DifferingOperand = DiffOp; 100 101 // If this differs in the same operand as the rest of the instructions in 102 // this class, move it to the SimilarInsts list. 103 if (DifferingOperand == DiffOp || DiffOp == ~0U) { 104 SimilarInsts.push_back(Insts[i-1]); 105 Insts.erase(Insts.begin()+i-1); 106 } 107 } 108 } 109 110 O << " case " << FirstInst.CGI->Namespace << "::" 111 << FirstInst.CGI->TheDef->getName() << ":\n"; 112 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) 113 O << " case " << SimilarInsts[i].CGI->Namespace << "::" 114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; 115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 116 if (i != DifferingOperand) { 117 // If the operand is the same for all instructions, just print it. 118 O << " " << FirstInst.Operands[i].getCode(); 119 } else { 120 // If this is the operand that varies between all of the instructions, 121 // emit a switch for just this operand now. 122 O << " switch (MI->getOpcode()) {\n"; 123 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint; 124 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 125 FirstInst.CGI->TheDef->getName(), 126 FirstInst.Operands[i])); 127 128 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { 129 AsmWriterInst &AWI = SimilarInsts[si]; 130 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ 131 AWI.CGI->TheDef->getName(), 132 AWI.Operands[i])); 133 } 134 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 135 while (!OpsToPrint.empty()) 136 PrintCases(OpsToPrint, O); 137 O << " }"; 138 } 139 O << "\n"; 140 } 141 O << " break;\n"; 142 } 143 144 void AsmWriterEmitter:: 145 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 146 std::vector<unsigned> &InstIdxs, 147 std::vector<unsigned> &InstOpsUsed) const { 148 InstIdxs.assign(NumberedInstructions->size(), ~0U); 149 150 // This vector parallels UniqueOperandCommands, keeping track of which 151 // instructions each case are used for. It is a comma separated string of 152 // enums. 153 std::vector<std::string> InstrsForCase; 154 InstrsForCase.resize(UniqueOperandCommands.size()); 155 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 156 157 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 158 const AsmWriterInst *Inst = getAsmWriterInstByID(i); 159 if (!Inst) 160 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc. 161 162 std::string Command; 163 if (Inst->Operands.empty()) 164 continue; // Instruction already done. 165 166 Command = " " + Inst->Operands[0].getCode() + "\n"; 167 168 // Check to see if we already have 'Command' in UniqueOperandCommands. 169 // If not, add it. 170 bool FoundIt = false; 171 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx) 172 if (UniqueOperandCommands[idx] == Command) { 173 InstIdxs[i] = idx; 174 InstrsForCase[idx] += ", "; 175 InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 176 FoundIt = true; 177 break; 178 } 179 if (!FoundIt) { 180 InstIdxs[i] = UniqueOperandCommands.size(); 181 UniqueOperandCommands.push_back(Command); 182 InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 183 184 // This command matches one operand so far. 185 InstOpsUsed.push_back(1); 186 } 187 } 188 189 // For each entry of UniqueOperandCommands, there is a set of instructions 190 // that uses it. If the next command of all instructions in the set are 191 // identical, fold it into the command. 192 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size(); 193 CommandIdx != e; ++CommandIdx) { 194 195 for (unsigned Op = 1; ; ++Op) { 196 // Scan for the first instruction in the set. 197 std::vector<unsigned>::iterator NIT = 198 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx); 199 if (NIT == InstIdxs.end()) break; // No commonality. 200 201 // If this instruction has no more operands, we isn't anything to merge 202 // into this command. 203 const AsmWriterInst *FirstInst = 204 getAsmWriterInstByID(NIT-InstIdxs.begin()); 205 if (!FirstInst || FirstInst->Operands.size() == Op) 206 break; 207 208 // Otherwise, scan to see if all of the other instructions in this command 209 // set share the operand. 210 bool AllSame = true; 211 212 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); 213 NIT != InstIdxs.end(); 214 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) { 215 // Okay, found another instruction in this command set. If the operand 216 // matches, we're ok, otherwise bail out. 217 const AsmWriterInst *OtherInst = 218 getAsmWriterInstByID(NIT-InstIdxs.begin()); 219 220 if (!OtherInst || OtherInst->Operands.size() == Op || 221 OtherInst->Operands[Op] != FirstInst->Operands[Op]) { 222 AllSame = false; 223 break; 224 } 225 } 226 if (!AllSame) break; 227 228 // Okay, everything in this command set has the same next operand. Add it 229 // to UniqueOperandCommands and remember that it was consumed. 230 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; 231 232 UniqueOperandCommands[CommandIdx] += Command; 233 InstOpsUsed[CommandIdx]++; 234 } 235 } 236 237 // Prepend some of the instructions each case is used for onto the case val. 238 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 239 std::string Instrs = InstrsForCase[i]; 240 if (Instrs.size() > 70) { 241 Instrs.erase(Instrs.begin()+70, Instrs.end()); 242 Instrs += "..."; 243 } 244 245 if (!Instrs.empty()) 246 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 247 UniqueOperandCommands[i]; 248 } 249 } 250 251 252 static void UnescapeString(std::string &Str) { 253 for (unsigned i = 0; i != Str.size(); ++i) { 254 if (Str[i] == '\\' && i != Str.size()-1) { 255 switch (Str[i+1]) { 256 default: continue; // Don't execute the code after the switch. 257 case 'a': Str[i] = '\a'; break; 258 case 'b': Str[i] = '\b'; break; 259 case 'e': Str[i] = 27; break; 260 case 'f': Str[i] = '\f'; break; 261 case 'n': Str[i] = '\n'; break; 262 case 'r': Str[i] = '\r'; break; 263 case 't': Str[i] = '\t'; break; 264 case 'v': Str[i] = '\v'; break; 265 case '"': Str[i] = '\"'; break; 266 case '\'': Str[i] = '\''; break; 267 case '\\': Str[i] = '\\'; break; 268 } 269 // Nuke the second character. 270 Str.erase(Str.begin()+i+1); 271 } 272 } 273 } 274 275 /// EmitPrintInstruction - Generate the code for the "printInstruction" method 276 /// implementation. Destroys all instances of AsmWriterInst information, by 277 /// clearing the Instructions vector. 278 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 279 Record *AsmWriter = Target.getAsmWriter(); 280 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 281 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 282 283 O << 284 "/// printInstruction - This method is automatically generated by tablegen\n" 285 "/// from the instruction set description.\n" 286 "void " << Target.getName() << ClassName 287 << "::printInstruction(const MCInst *MI, " 288 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 289 << "raw_ostream &O) {\n"; 290 291 // Build an aggregate string, and build a table of offsets into it. 292 SequenceToOffsetTable<std::string> StringTable; 293 294 /// OpcodeInfo - This encodes the index of the string to use for the first 295 /// chunk of the output as well as indices used for operand printing. 296 /// To reduce the number of unhandled cases, we expand the size from 32-bit 297 /// to 32+16 = 48-bit. 298 std::vector<uint64_t> OpcodeInfo; 299 300 // Add all strings to the string table upfront so it can generate an optimized 301 // representation. 302 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 303 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 304 if (AWI && 305 AWI->Operands[0].OperandType == 306 AsmWriterOperand::isLiteralTextOperand && 307 !AWI->Operands[0].Str.empty()) { 308 std::string Str = AWI->Operands[0].Str; 309 UnescapeString(Str); 310 StringTable.add(Str); 311 } 312 } 313 314 StringTable.layout(); 315 316 unsigned MaxStringIdx = 0; 317 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 318 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 319 unsigned Idx; 320 if (!AWI) { 321 // Something not handled by the asmwriter printer. 322 Idx = ~0U; 323 } else if (AWI->Operands[0].OperandType != 324 AsmWriterOperand::isLiteralTextOperand || 325 AWI->Operands[0].Str.empty()) { 326 // Something handled by the asmwriter printer, but with no leading string. 327 Idx = StringTable.get(""); 328 } else { 329 std::string Str = AWI->Operands[0].Str; 330 UnescapeString(Str); 331 Idx = StringTable.get(Str); 332 MaxStringIdx = std::max(MaxStringIdx, Idx); 333 334 // Nuke the string from the operand list. It is now handled! 335 AWI->Operands.erase(AWI->Operands.begin()); 336 } 337 338 // Bias offset by one since we want 0 as a sentinel. 339 OpcodeInfo.push_back(Idx+1); 340 } 341 342 // Figure out how many bits we used for the string index. 343 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 344 345 // To reduce code size, we compactify common instructions into a few bits 346 // in the opcode-indexed table. 347 unsigned BitsLeft = 64-AsmStrBits; 348 349 std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 350 351 while (1) { 352 std::vector<std::string> UniqueOperandCommands; 353 std::vector<unsigned> InstIdxs; 354 std::vector<unsigned> NumInstOpsHandled; 355 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 356 NumInstOpsHandled); 357 358 // If we ran out of operands to print, we're done. 359 if (UniqueOperandCommands.empty()) break; 360 361 // Compute the number of bits we need to represent these cases, this is 362 // ceil(log2(numentries)). 363 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 364 365 // If we don't have enough bits for this operand, don't include it. 366 if (NumBits > BitsLeft) { 367 DEBUG(errs() << "Not enough bits to densely encode " << NumBits 368 << " more bits\n"); 369 break; 370 } 371 372 // Otherwise, we can include this in the initial lookup table. Add it in. 373 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) 374 if (InstIdxs[i] != ~0U) { 375 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); 376 } 377 BitsLeft -= NumBits; 378 379 // Remove the info about this operand. 380 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 381 if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) 382 if (!Inst->Operands.empty()) { 383 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; 384 assert(NumOps <= Inst->Operands.size() && 385 "Can't remove this many ops!"); 386 Inst->Operands.erase(Inst->Operands.begin(), 387 Inst->Operands.begin()+NumOps); 388 } 389 } 390 391 // Remember the handlers for this set of operands. 392 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); 393 } 394 395 396 // We always emit at least one 32-bit table. A second table is emitted if 397 // more bits are needed. 398 O<<" static const uint32_t OpInfo[] = {\n"; 399 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 400 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " 401 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 402 } 403 // Add a dummy entry so the array init doesn't end with a comma. 404 O << " 0U\n"; 405 O << " };\n\n"; 406 407 if (BitsLeft < 32) { 408 // Add a second OpInfo table only when it is necessary. 409 // Adjust the type of the second table based on the number of bits needed. 410 O << " static const uint" 411 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") 412 << "_t OpInfo2[] = {\n"; 413 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 414 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " 415 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 416 } 417 // Add a dummy entry so the array init doesn't end with a comma. 418 O << " 0U\n"; 419 O << " };\n\n"; 420 } 421 422 // Emit the string itself. 423 O << " static const char AsmStrs[] = {\n"; 424 StringTable.emit(O, printChar); 425 O << " };\n\n"; 426 427 O << " O << \"\\t\";\n\n"; 428 429 O << " // Emit the opcode for the instruction.\n"; 430 if (BitsLeft < 32) { 431 // If we have two tables then we need to perform two lookups and combine 432 // the results into a single 64-bit value. 433 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n" 434 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n" 435 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n"; 436 } else { 437 // If only one table is used we just need to perform a single lookup. 438 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n"; 439 } 440 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 441 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 442 443 // Output the table driven operand information. 444 BitsLeft = 64-AsmStrBits; 445 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 446 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 447 448 // Compute the number of bits we need to represent these cases, this is 449 // ceil(log2(numentries)). 450 unsigned NumBits = Log2_32_Ceil(Commands.size()); 451 assert(NumBits <= BitsLeft && "consistency error"); 452 453 // Emit code to extract this field from Bits. 454 O << "\n // Fragment " << i << " encoded into " << NumBits 455 << " bits for " << Commands.size() << " unique commands.\n"; 456 457 if (Commands.size() == 2) { 458 // Emit two possibilitys with if/else. 459 O << " if ((Bits >> " 460 << (64-BitsLeft) << ") & " 461 << ((1 << NumBits)-1) << ") {\n" 462 << Commands[1] 463 << " } else {\n" 464 << Commands[0] 465 << " }\n\n"; 466 } else if (Commands.size() == 1) { 467 // Emit a single possibility. 468 O << Commands[0] << "\n\n"; 469 } else { 470 O << " switch ((Bits >> " 471 << (64-BitsLeft) << ") & " 472 << ((1 << NumBits)-1) << ") {\n" 473 << " default: llvm_unreachable(\"Invalid command number.\");\n"; 474 475 // Print out all the cases. 476 for (unsigned i = 0, e = Commands.size(); i != e; ++i) { 477 O << " case " << i << ":\n"; 478 O << Commands[i]; 479 O << " break;\n"; 480 } 481 O << " }\n\n"; 482 } 483 BitsLeft -= NumBits; 484 } 485 486 // Okay, delete instructions with no operand info left. 487 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { 488 // Entire instruction has been emitted? 489 AsmWriterInst &Inst = Instructions[i]; 490 if (Inst.Operands.empty()) { 491 Instructions.erase(Instructions.begin()+i); 492 --i; --e; 493 } 494 } 495 496 497 // Because this is a vector, we want to emit from the end. Reverse all of the 498 // elements in the vector. 499 std::reverse(Instructions.begin(), Instructions.end()); 500 501 502 // Now that we've emitted all of the operand info that fit into 32 bits, emit 503 // information for those instructions that are left. This is a less dense 504 // encoding, but we expect the main 32-bit table to handle the majority of 505 // instructions. 506 if (!Instructions.empty()) { 507 // Find the opcode # of inline asm. 508 O << " switch (MI->getOpcode()) {\n"; 509 while (!Instructions.empty()) 510 EmitInstructions(Instructions, O); 511 512 O << " }\n"; 513 O << " return;\n"; 514 } 515 516 O << "}\n"; 517 } 518 519 static const char *getMinimalTypeForRange(uint64_t Range) { 520 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 521 if (Range > 0xFFFF) 522 return "uint32_t"; 523 if (Range > 0xFF) 524 return "uint16_t"; 525 return "uint8_t"; 526 } 527 528 static void 529 emitRegisterNameString(raw_ostream &O, StringRef AltName, 530 const std::deque<CodeGenRegister> &Registers) { 531 SequenceToOffsetTable<std::string> StringTable; 532 SmallVector<std::string, 4> AsmNames(Registers.size()); 533 unsigned i = 0; 534 for (const auto &Reg : Registers) { 535 std::string &AsmName = AsmNames[i++]; 536 537 // "NoRegAltName" is special. We don't need to do a lookup for that, 538 // as it's just a reference to the default register name. 539 if (AltName == "" || AltName == "NoRegAltName") { 540 AsmName = Reg.TheDef->getValueAsString("AsmName"); 541 if (AsmName.empty()) 542 AsmName = Reg.getName(); 543 } else { 544 // Make sure the register has an alternate name for this index. 545 std::vector<Record*> AltNameList = 546 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 547 unsigned Idx = 0, e; 548 for (e = AltNameList.size(); 549 Idx < e && (AltNameList[Idx]->getName() != AltName); 550 ++Idx) 551 ; 552 // If the register has an alternate name for this index, use it. 553 // Otherwise, leave it empty as an error flag. 554 if (Idx < e) { 555 std::vector<std::string> AltNames = 556 Reg.TheDef->getValueAsListOfStrings("AltNames"); 557 if (AltNames.size() <= Idx) 558 PrintFatalError(Reg.TheDef->getLoc(), 559 "Register definition missing alt name for '" + 560 AltName + "'."); 561 AsmName = AltNames[Idx]; 562 } 563 } 564 StringTable.add(AsmName); 565 } 566 567 StringTable.layout(); 568 O << " static const char AsmStrs" << AltName << "[] = {\n"; 569 StringTable.emit(O, printChar); 570 O << " };\n\n"; 571 572 O << " static const " << getMinimalTypeForRange(StringTable.size()-1) 573 << " RegAsmOffset" << AltName << "[] = {"; 574 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 575 if ((i % 14) == 0) 576 O << "\n "; 577 O << StringTable.get(AsmNames[i]) << ", "; 578 } 579 O << "\n };\n" 580 << "\n"; 581 } 582 583 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 584 Record *AsmWriter = Target.getAsmWriter(); 585 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 586 const auto &Registers = Target.getRegBank().getRegisters(); 587 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices(); 588 bool hasAltNames = AltNameIndices.size() > 1; 589 std::string Namespace = 590 Registers.front().TheDef->getValueAsString("Namespace"); 591 592 O << 593 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 594 "/// from the register set description. This returns the assembler name\n" 595 "/// for the specified register.\n" 596 "const char *" << Target.getName() << ClassName << "::"; 597 if (hasAltNames) 598 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 599 else 600 O << "getRegisterName(unsigned RegNo) {\n"; 601 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 602 << " && \"Invalid register number!\");\n" 603 << "\n"; 604 605 if (hasAltNames) { 606 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) 607 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers); 608 } else 609 emitRegisterNameString(O, "", Registers); 610 611 if (hasAltNames) { 612 O << " switch(AltIdx) {\n" 613 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 614 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { 615 std::string AltName(AltNameIndices[i]->getName()); 616 std::string Prefix = !Namespace.empty() ? Namespace + "::" : ""; 617 O << " case " << Prefix << AltName << ":\n" 618 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" 619 << AltName << "[RegNo-1]) &&\n" 620 << " \"Invalid alt name index for register!\");\n" 621 << " return AsmStrs" << AltName << "+RegAsmOffset" 622 << AltName << "[RegNo-1];\n"; 623 } 624 O << " }\n"; 625 } else { 626 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 627 << " \"Invalid alt name index for register!\");\n" 628 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 629 } 630 O << "}\n"; 631 } 632 633 namespace { 634 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if 635 // they both have the same conditionals. In which case, we cannot print out the 636 // alias for that pattern. 637 class IAPrinter { 638 std::vector<std::string> Conds; 639 std::map<StringRef, std::pair<int, int>> OpMap; 640 SmallVector<Record*, 4> ReqFeatures; 641 642 std::string Result; 643 std::string AsmString; 644 public: 645 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {} 646 647 void addCond(const std::string &C) { Conds.push_back(C); } 648 649 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 650 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 651 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 652 "Idx out of range"); 653 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 654 } 655 656 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 657 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 658 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 659 660 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 661 StringRef::iterator End) { 662 StringRef::iterator I = Start; 663 StringRef::iterator Next; 664 if (*I == '{') { 665 // ${some_name} 666 Start = ++I; 667 while (I != End && *I != '}') 668 ++I; 669 Next = I; 670 // eat the final '}' 671 if (Next != End) 672 ++Next; 673 } else { 674 // $name, just eat the usual suspects. 675 while (I != End && 676 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || 677 (*I >= '0' && *I <= '9') || *I == '_')) 678 ++I; 679 Next = I; 680 } 681 682 return std::make_pair(StringRef(Start, I - Start), Next); 683 } 684 685 void print(raw_ostream &O) { 686 if (Conds.empty() && ReqFeatures.empty()) { 687 O.indent(6) << "return true;\n"; 688 return; 689 } 690 691 O << "if ("; 692 693 for (std::vector<std::string>::iterator 694 I = Conds.begin(), E = Conds.end(); I != E; ++I) { 695 if (I != Conds.begin()) { 696 O << " &&\n"; 697 O.indent(8); 698 } 699 700 O << *I; 701 } 702 703 O << ") {\n"; 704 O.indent(6) << "// " << Result << "\n"; 705 706 // Directly mangle mapped operands into the string. Each operand is 707 // identified by a '$' sign followed by a byte identifying the number of the 708 // operand. We add one to the index to avoid zero bytes. 709 StringRef ASM(AsmString); 710 SmallString<128> OutString; 711 raw_svector_ostream OS(OutString); 712 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 713 OS << *I; 714 if (*I == '$') { 715 StringRef Name; 716 std::tie(Name, I) = parseName(++I, E); 717 assert(isOpMapped(Name) && "Unmapped operand!"); 718 719 int OpIndex, PrintIndex; 720 std::tie(OpIndex, PrintIndex) = getOpData(Name); 721 if (PrintIndex == -1) { 722 // Can use the default printOperand route. 723 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 724 } else 725 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 726 // number, and which of our pre-detected Methods to call. 727 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 728 } else { 729 ++I; 730 } 731 } 732 733 // Emit the string. 734 O.indent(6) << "AsmString = \"" << OutString << "\";\n"; 735 736 O.indent(6) << "break;\n"; 737 O.indent(4) << '}'; 738 } 739 740 bool operator==(const IAPrinter &RHS) const { 741 if (Conds.size() != RHS.Conds.size()) 742 return false; 743 744 unsigned Idx = 0; 745 for (const auto &str : Conds) 746 if (str != RHS.Conds[Idx++]) 747 return false; 748 749 return true; 750 } 751 }; 752 753 } // end anonymous namespace 754 755 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 756 std::string FlatAsmString = 757 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); 758 AsmString = FlatAsmString; 759 760 return AsmString.count(' ') + AsmString.count('\t'); 761 } 762 763 namespace { 764 struct AliasPriorityComparator { 765 typedef std::pair<CodeGenInstAlias, int> ValueType; 766 bool operator()(const ValueType &LHS, const ValueType &RHS) { 767 if (LHS.second == RHS.second) { 768 // We don't actually care about the order, but for consistency it 769 // shouldn't depend on pointer comparisons. 770 return LHS.first.TheDef->getName() < RHS.first.TheDef->getName(); 771 } 772 773 // Aliases with larger priorities should be considered first. 774 return LHS.second > RHS.second; 775 } 776 }; 777 } 778 779 780 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 781 Record *AsmWriter = Target.getAsmWriter(); 782 783 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 784 O << "#undef PRINT_ALIAS_INSTR\n\n"; 785 786 ////////////////////////////// 787 // Gather information about aliases we need to print 788 ////////////////////////////// 789 790 // Emit the method that prints the alias instruction. 791 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 792 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 793 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 794 795 std::vector<Record*> AllInstAliases = 796 Records.getAllDerivedDefinitions("InstAlias"); 797 798 // Create a map from the qualified name to a list of potential matches. 799 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator> 800 AliasWithPriority; 801 std::map<std::string, AliasWithPriority> AliasMap; 802 for (std::vector<Record*>::iterator 803 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { 804 const Record *R = *I; 805 int Priority = R->getValueAsInt("EmitPriority"); 806 if (Priority < 1) 807 continue; // Aliases with priority 0 are never emitted. 808 809 const DagInit *DI = R->getValueAsDag("ResultInst"); 810 const DefInit *Op = cast<DefInit>(DI->getOperator()); 811 AliasMap[getQualifiedName(Op->getDef())].insert( 812 std::make_pair(CodeGenInstAlias(*I, Variant, Target), Priority)); 813 } 814 815 // A map of which conditions need to be met for each instruction operand 816 // before it can be matched to the mnemonic. 817 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap; 818 819 // A list of MCOperandPredicates for all operands in use, and the reverse map 820 std::vector<const Record*> MCOpPredicates; 821 DenseMap<const Record*, unsigned> MCOpPredicateMap; 822 823 for (auto &Aliases : AliasMap) { 824 for (auto &Alias : Aliases.second) { 825 const CodeGenInstAlias &CGA = Alias.first; 826 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 827 unsigned NumResultOps = 828 CountNumOperands(CGA.ResultInst->AsmString, Variant); 829 830 // Don't emit the alias if it has more operands than what it's aliasing. 831 if (NumResultOps < CountNumOperands(CGA.AsmString, Variant)) 832 continue; 833 834 IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); 835 836 unsigned NumMIOps = 0; 837 for (auto &Operand : CGA.ResultOperands) 838 NumMIOps += Operand.getMINumOperands(); 839 840 std::string Cond; 841 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); 842 IAP.addCond(Cond); 843 844 bool CantHandle = false; 845 846 unsigned MIOpNum = 0; 847 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 848 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; 849 850 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; 851 852 switch (RO.Kind) { 853 case CodeGenInstAlias::ResultOperand::K_Record: { 854 const Record *Rec = RO.getRecord(); 855 StringRef ROName = RO.getName(); 856 int PrintMethodIdx = -1; 857 858 // These two may have a PrintMethod, which we want to record (if it's 859 // the first time we've seen it) and provide an index for the aliasing 860 // code to use. 861 if (Rec->isSubClassOf("RegisterOperand") || 862 Rec->isSubClassOf("Operand")) { 863 std::string PrintMethod = Rec->getValueAsString("PrintMethod"); 864 if (PrintMethod != "" && PrintMethod != "printOperand") { 865 PrintMethodIdx = std::find(PrintMethods.begin(), 866 PrintMethods.end(), PrintMethod) - 867 PrintMethods.begin(); 868 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 869 PrintMethods.push_back(PrintMethod); 870 } 871 } 872 873 if (Rec->isSubClassOf("RegisterOperand")) 874 Rec = Rec->getValueAsDef("RegClass"); 875 if (Rec->isSubClassOf("RegisterClass")) { 876 IAP.addCond(Op + ".isReg()"); 877 878 if (!IAP.isOpMapped(ROName)) { 879 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 880 Record *R = CGA.ResultOperands[i].getRecord(); 881 if (R->isSubClassOf("RegisterOperand")) 882 R = R->getValueAsDef("RegClass"); 883 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + 884 R->getName() + "RegClassID)" 885 ".contains(" + Op + ".getReg())"; 886 } else { 887 Cond = Op + ".getReg() == MI->getOperand(" + 888 llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()"; 889 } 890 } else { 891 // Assume all printable operands are desired for now. This can be 892 // overridden in the InstAlias instantiation if necessary. 893 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 894 895 // There might be an additional predicate on the MCOperand 896 unsigned Entry = MCOpPredicateMap[Rec]; 897 if (!Entry) { 898 if (!Rec->isValueUnset("MCOperandPredicate")) { 899 MCOpPredicates.push_back(Rec); 900 Entry = MCOpPredicates.size(); 901 MCOpPredicateMap[Rec] = Entry; 902 } else 903 break; // No conditions on this operand at all 904 } 905 Cond = Target.getName() + ClassName + "ValidateMCOperand(" + 906 Op + ", STI, " + llvm::utostr(Entry) + ")"; 907 } 908 // for all subcases of ResultOperand::K_Record: 909 IAP.addCond(Cond); 910 break; 911 } 912 case CodeGenInstAlias::ResultOperand::K_Imm: { 913 // Just because the alias has an immediate result, doesn't mean the 914 // MCInst will. An MCExpr could be present, for example. 915 IAP.addCond(Op + ".isImm()"); 916 917 Cond = Op + ".getImm() == " + 918 llvm::utostr(CGA.ResultOperands[i].getImm()); 919 IAP.addCond(Cond); 920 break; 921 } 922 case CodeGenInstAlias::ResultOperand::K_Reg: 923 // If this is zero_reg, something's playing tricks we're not 924 // equipped to handle. 925 if (!CGA.ResultOperands[i].getRegister()) { 926 CantHandle = true; 927 break; 928 } 929 930 Cond = Op + ".getReg() == " + Target.getName() + "::" + 931 CGA.ResultOperands[i].getRegister()->getName(); 932 IAP.addCond(Cond); 933 break; 934 } 935 936 MIOpNum += RO.getMINumOperands(); 937 } 938 939 if (CantHandle) continue; 940 IAPrinterMap[Aliases.first].push_back(std::move(IAP)); 941 } 942 } 943 944 ////////////////////////////// 945 // Write out the printAliasInstr function 946 ////////////////////////////// 947 948 std::string Header; 949 raw_string_ostream HeaderO(Header); 950 951 HeaderO << "bool " << Target.getName() << ClassName 952 << "::printAliasInstr(const MCInst" 953 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 954 << "raw_ostream &OS) {\n"; 955 956 std::string Cases; 957 raw_string_ostream CasesO(Cases); 958 959 for (auto &Entry : IAPrinterMap) { 960 std::vector<IAPrinter> &IAPs = Entry.second; 961 std::vector<IAPrinter*> UniqueIAPs; 962 963 for (auto &LHS : IAPs) { 964 bool IsDup = false; 965 for (const auto &RHS : IAPs) { 966 if (&LHS != &RHS && LHS == RHS) { 967 IsDup = true; 968 break; 969 } 970 } 971 972 if (!IsDup) 973 UniqueIAPs.push_back(&LHS); 974 } 975 976 if (UniqueIAPs.empty()) continue; 977 978 CasesO.indent(2) << "case " << Entry.first << ":\n"; 979 980 for (std::vector<IAPrinter*>::iterator 981 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { 982 IAPrinter *IAP = *II; 983 CasesO.indent(4); 984 IAP->print(CasesO); 985 CasesO << '\n'; 986 } 987 988 CasesO.indent(4) << "return false;\n"; 989 } 990 991 if (CasesO.str().empty()) { 992 O << HeaderO.str(); 993 O << " return false;\n"; 994 O << "}\n\n"; 995 O << "#endif // PRINT_ALIAS_INSTR\n"; 996 return; 997 } 998 999 if (!MCOpPredicates.empty()) 1000 O << "static bool " << Target.getName() << ClassName 1001 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1002 << " const MCSubtargetInfo &STI,\n" 1003 << " unsigned PredicateIndex);\n"; 1004 1005 O << HeaderO.str(); 1006 O.indent(2) << "const char *AsmString;\n"; 1007 O.indent(2) << "switch (MI->getOpcode()) {\n"; 1008 O.indent(2) << "default: return false;\n"; 1009 O << CasesO.str(); 1010 O.indent(2) << "}\n\n"; 1011 1012 // Code that prints the alias, replacing the operands with the ones from the 1013 // MCInst. 1014 O << " unsigned I = 0;\n"; 1015 O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n"; 1016 O << " AsmString[I] != '\\0')\n"; 1017 O << " ++I;\n"; 1018 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 1019 1020 O << " if (AsmString[I] != '\\0') {\n"; 1021 O << " OS << '\\t';\n"; 1022 O << " do {\n"; 1023 O << " if (AsmString[I] == '$') {\n"; 1024 O << " ++I;\n"; 1025 O << " if (AsmString[I] == (char)0xff) {\n"; 1026 O << " ++I;\n"; 1027 O << " int OpIdx = AsmString[I++] - 1;\n"; 1028 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1029 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; 1030 O << (PassSubtarget ? "STI, " : ""); 1031 O << "OS);\n"; 1032 O << " } else\n"; 1033 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; 1034 O << (PassSubtarget ? "STI, " : ""); 1035 O << "OS);\n"; 1036 O << " } else {\n"; 1037 O << " OS << AsmString[I++];\n"; 1038 O << " }\n"; 1039 O << " } while (AsmString[I] != '\\0');\n"; 1040 O << " }\n\n"; 1041 1042 O << " return true;\n"; 1043 O << "}\n\n"; 1044 1045 ////////////////////////////// 1046 // Write out the printCustomAliasOperand function 1047 ////////////////////////////// 1048 1049 O << "void " << Target.getName() << ClassName << "::" 1050 << "printCustomAliasOperand(\n" 1051 << " const MCInst *MI, unsigned OpIdx,\n" 1052 << " unsigned PrintMethodIdx,\n" 1053 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") 1054 << " raw_ostream &OS) {\n"; 1055 if (PrintMethods.empty()) 1056 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1057 else { 1058 O << " switch (PrintMethodIdx) {\n" 1059 << " default:\n" 1060 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1061 << " break;\n"; 1062 1063 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1064 O << " case " << i << ":\n" 1065 << " " << PrintMethods[i] << "(MI, OpIdx, " 1066 << (PassSubtarget ? "STI, " : "") << "OS);\n" 1067 << " break;\n"; 1068 } 1069 O << " }\n"; 1070 } 1071 O << "}\n\n"; 1072 1073 if (!MCOpPredicates.empty()) { 1074 O << "static bool " << Target.getName() << ClassName 1075 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1076 << " const MCSubtargetInfo &STI,\n" 1077 << " unsigned PredicateIndex) {\n" 1078 << " switch (PredicateIndex) {\n" 1079 << " default:\n" 1080 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" 1081 << " break;\n"; 1082 1083 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { 1084 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate"); 1085 if (StringInit *SI = dyn_cast<StringInit>(MCOpPred)) { 1086 O << " case " << i + 1 << ": {\n" 1087 << SI->getValue() << "\n" 1088 << " }\n"; 1089 } else 1090 llvm_unreachable("Unexpected MCOperandPredicate field!"); 1091 } 1092 O << " }\n" 1093 << "}\n\n"; 1094 } 1095 1096 O << "#endif // PRINT_ALIAS_INSTR\n"; 1097 } 1098 1099 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1100 Record *AsmWriter = Target.getAsmWriter(); 1101 for (const CodeGenInstruction *I : Target.instructions()) 1102 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") 1103 Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"), 1104 AsmWriter->getValueAsInt("PassSubtarget")); 1105 1106 // Get the instruction numbering. 1107 NumberedInstructions = &Target.getInstructionsByEnumValue(); 1108 1109 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not 1110 // all machine instructions are necessarily being printed, so there may be 1111 // target instructions not in this map. 1112 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) 1113 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); 1114 } 1115 1116 void AsmWriterEmitter::run(raw_ostream &O) { 1117 EmitPrintInstruction(O); 1118 EmitGetRegisterName(O); 1119 EmitPrintAliasInstruction(O); 1120 } 1121 1122 1123 namespace llvm { 1124 1125 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1126 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1127 AsmWriterEmitter(RK).run(OS); 1128 } 1129 1130 } // End llvm namespace 1131