1 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_MIPS_CONSTANTS_H_ 6 #define V8_MIPS_CONSTANTS_H_ 7 #include "src/globals.h" 8 // UNIMPLEMENTED_ macro for MIPS. 9 #ifdef DEBUG 10 #define UNIMPLEMENTED_MIPS() \ 11 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ 12 __FILE__, __LINE__, __func__) 13 #else 14 #define UNIMPLEMENTED_MIPS() 15 #endif 16 17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n") 18 19 enum ArchVariants { 20 kMips32r1 = v8::internal::MIPSr1, 21 kMips32r2 = v8::internal::MIPSr2, 22 kMips32r6 = v8::internal::MIPSr6, 23 kLoongson 24 }; 25 26 #ifdef _MIPS_ARCH_MIPS32R2 27 static const ArchVariants kArchVariant = kMips32r2; 28 #elif _MIPS_ARCH_MIPS32R6 29 static const ArchVariants kArchVariant = kMips32r6; 30 #elif _MIPS_ARCH_LOONGSON 31 // The loongson flag refers to the LOONGSON architectures based on MIPS-III, 32 // which predates (and is a subset of) the mips32r2 and r1 architectures. 33 static const ArchVariants kArchVariant = kLoongson; 34 #elif _MIPS_ARCH_MIPS32RX 35 // This flags referred to compatibility mode that creates universal code that 36 // can run on any MIPS32 architecture revision. The dynamically generated code 37 // by v8 is specialized for the MIPS host detected in runtime probing. 38 static const ArchVariants kArchVariant = kMips32r1; 39 #else 40 static const ArchVariants kArchVariant = kMips32r1; 41 #endif 42 43 enum Endianness { 44 kLittle, 45 kBig 46 }; 47 48 #if defined(V8_TARGET_LITTLE_ENDIAN) 49 static const Endianness kArchEndian = kLittle; 50 #elif defined(V8_TARGET_BIG_ENDIAN) 51 static const Endianness kArchEndian = kBig; 52 #else 53 #error Unknown endianness 54 #endif 55 56 enum FpuMode { 57 kFP32, 58 kFP64, 59 kFPXX 60 }; 61 62 #if defined(FPU_MODE_FP32) 63 static const FpuMode kFpuMode = kFP32; 64 #elif defined(FPU_MODE_FP64) 65 static const FpuMode kFpuMode = kFP64; 66 #elif defined(FPU_MODE_FPXX) 67 static const FpuMode kFpuMode = kFPXX; 68 #else 69 static const FpuMode kFpuMode = kFP32; 70 #endif 71 72 #if(defined(__mips_hard_float) && __mips_hard_float != 0) 73 // Use floating-point coprocessor instructions. This flag is raised when 74 // -mhard-float is passed to the compiler. 75 const bool IsMipsSoftFloatABI = false; 76 #elif(defined(__mips_soft_float) && __mips_soft_float != 0) 77 // This flag is raised when -msoft-float is passed to the compiler. 78 // Although FPU is a base requirement for v8, soft-float ABI is used 79 // on soft-float systems with FPU kernel emulation. 80 const bool IsMipsSoftFloatABI = true; 81 #else 82 const bool IsMipsSoftFloatABI = true; 83 #endif 84 85 #if defined(V8_TARGET_LITTLE_ENDIAN) 86 const uint32_t kHoleNanUpper32Offset = 4; 87 const uint32_t kHoleNanLower32Offset = 0; 88 #elif defined(V8_TARGET_BIG_ENDIAN) 89 const uint32_t kHoleNanUpper32Offset = 0; 90 const uint32_t kHoleNanLower32Offset = 4; 91 #else 92 #error Unknown endianness 93 #endif 94 95 #ifndef FPU_MODE_FPXX 96 #define IsFp64Mode() \ 97 (kFpuMode == kFP64) 98 #else 99 #define IsFp64Mode() \ 100 (CpuFeatures::IsSupported(FP64FPU)) 101 #endif 102 103 #ifndef _MIPS_ARCH_MIPS32RX 104 #define IsMipsArchVariant(check) \ 105 (kArchVariant == check) 106 #else 107 #define IsMipsArchVariant(check) \ 108 (CpuFeatures::IsSupported(static_cast<CpuFeature>(check))) 109 #endif 110 111 112 #define __STDC_FORMAT_MACROS 113 #include <inttypes.h> 114 115 // Defines constants and accessor classes to assemble, disassemble and 116 // simulate MIPS32 instructions. 117 // 118 // See: MIPS32 Architecture For Programmers 119 // Volume II: The MIPS32 Instruction Set 120 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. 121 122 namespace v8 { 123 namespace internal { 124 125 // ----------------------------------------------------------------------------- 126 // Registers and FPURegisters. 127 128 // Number of general purpose registers. 129 const int kNumRegisters = 32; 130 const int kInvalidRegister = -1; 131 132 // Number of registers with HI, LO, and pc. 133 const int kNumSimuRegisters = 35; 134 135 // In the simulator, the PC register is simulated as the 34th register. 136 const int kPCRegister = 34; 137 138 // Number coprocessor registers. 139 const int kNumFPURegisters = 32; 140 const int kInvalidFPURegister = -1; 141 142 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. 143 const int kFCSRRegister = 31; 144 const int kInvalidFPUControlRegister = -1; 145 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; 146 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31); 147 const uint64_t kFPU64InvalidResult = 148 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1; 149 const int64_t kFPU64InvalidResultNegative = 150 static_cast<int64_t>(static_cast<uint64_t>(1) << 63); 151 152 // FCSR constants. 153 const uint32_t kFCSRInexactFlagBit = 2; 154 const uint32_t kFCSRUnderflowFlagBit = 3; 155 const uint32_t kFCSROverflowFlagBit = 4; 156 const uint32_t kFCSRDivideByZeroFlagBit = 5; 157 const uint32_t kFCSRInvalidOpFlagBit = 6; 158 const uint32_t kFCSRNaN2008FlagBit = 18; 159 160 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit; 161 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit; 162 const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit; 163 const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit; 164 const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit; 165 const uint32_t kFCSRNaN2008FlagMask = 1 << kFCSRNaN2008FlagBit; 166 167 const uint32_t kFCSRFlagMask = 168 kFCSRInexactFlagMask | 169 kFCSRUnderflowFlagMask | 170 kFCSROverflowFlagMask | 171 kFCSRDivideByZeroFlagMask | 172 kFCSRInvalidOpFlagMask; 173 174 const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^ kFCSRInexactFlagMask; 175 176 // 'pref' instruction hints 177 const int32_t kPrefHintLoad = 0; 178 const int32_t kPrefHintStore = 1; 179 const int32_t kPrefHintLoadStreamed = 4; 180 const int32_t kPrefHintStoreStreamed = 5; 181 const int32_t kPrefHintLoadRetained = 6; 182 const int32_t kPrefHintStoreRetained = 7; 183 const int32_t kPrefHintWritebackInvalidate = 25; 184 const int32_t kPrefHintPrepareForStore = 30; 185 186 // Helper functions for converting between register numbers and names. 187 class Registers { 188 public: 189 // Return the name of the register. 190 static const char* Name(int reg); 191 192 // Lookup the register number for the name provided. 193 static int Number(const char* name); 194 195 struct RegisterAlias { 196 int reg; 197 const char* name; 198 }; 199 200 static const int32_t kMaxValue = 0x7fffffff; 201 static const int32_t kMinValue = 0x80000000; 202 203 private: 204 static const char* names_[kNumSimuRegisters]; 205 static const RegisterAlias aliases_[]; 206 }; 207 208 // Helper functions for converting between register numbers and names. 209 class FPURegisters { 210 public: 211 // Return the name of the register. 212 static const char* Name(int reg); 213 214 // Lookup the register number for the name provided. 215 static int Number(const char* name); 216 217 struct RegisterAlias { 218 int creg; 219 const char* name; 220 }; 221 222 private: 223 static const char* names_[kNumFPURegisters]; 224 static const RegisterAlias aliases_[]; 225 }; 226 227 228 // ----------------------------------------------------------------------------- 229 // Instructions encoding constants. 230 231 // On MIPS all instructions are 32 bits. 232 typedef int32_t Instr; 233 234 // Special Software Interrupt codes when used in the presence of the MIPS 235 // simulator. 236 enum SoftwareInterruptCodes { 237 // Transition to C code. 238 call_rt_redirected = 0xfffff 239 }; 240 241 // On MIPS Simulator breakpoints can have different codes: 242 // - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints, 243 // the simulator will run through them and print the registers. 244 // - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop() 245 // instructions (see Assembler::stop()). 246 // - Breaks larger than kMaxStopCode are simple breaks, dropping you into the 247 // debugger. 248 const uint32_t kMaxWatchpointCode = 31; 249 const uint32_t kMaxStopCode = 127; 250 STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode); 251 252 253 // ----- Fields offset and length. 254 const int kOpcodeShift = 26; 255 const int kOpcodeBits = 6; 256 const int kRsShift = 21; 257 const int kRsBits = 5; 258 const int kRtShift = 16; 259 const int kRtBits = 5; 260 const int kRdShift = 11; 261 const int kRdBits = 5; 262 const int kSaShift = 6; 263 const int kSaBits = 5; 264 const int kLsaSaBits = 2; 265 const int kFunctionShift = 0; 266 const int kFunctionBits = 6; 267 const int kLuiShift = 16; 268 const int kBp2Shift = 6; 269 const int kBp2Bits = 2; 270 271 const int kImm16Shift = 0; 272 const int kImm16Bits = 16; 273 const int kImm18Shift = 0; 274 const int kImm18Bits = 18; 275 const int kImm19Shift = 0; 276 const int kImm19Bits = 19; 277 const int kImm21Shift = 0; 278 const int kImm21Bits = 21; 279 const int kImm26Shift = 0; 280 const int kImm26Bits = 26; 281 const int kImm28Shift = 0; 282 const int kImm28Bits = 28; 283 const int kImm32Shift = 0; 284 const int kImm32Bits = 32; 285 286 // In branches and jumps immediate fields point to words, not bytes, 287 // and are therefore shifted by 2. 288 const int kImmFieldShift = 2; 289 290 const int kFrBits = 5; 291 const int kFrShift = 21; 292 const int kFsShift = 11; 293 const int kFsBits = 5; 294 const int kFtShift = 16; 295 const int kFtBits = 5; 296 const int kFdShift = 6; 297 const int kFdBits = 5; 298 const int kFCccShift = 8; 299 const int kFCccBits = 3; 300 const int kFBccShift = 18; 301 const int kFBccBits = 3; 302 const int kFBtrueShift = 16; 303 const int kFBtrueBits = 1; 304 305 // ----- Miscellaneous useful masks. 306 // Instruction bit masks. 307 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; 308 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; 309 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift; 310 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift; 311 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift; 312 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; 313 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift; 314 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; 315 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; 316 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; 317 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; 318 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift; 319 // Misc masks. 320 const int kHiMask = 0xffff << 16; 321 const int kLoMask = 0xffff; 322 const int kSignMask = 0x80000000; 323 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1; 324 325 // ----- MIPS Opcodes and Function Fields. 326 // We use this presentation to stay close to the table representation in 327 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set. 328 enum Opcode : uint32_t { 329 SPECIAL = 0U << kOpcodeShift, 330 REGIMM = 1U << kOpcodeShift, 331 332 J = ((0U << 3) + 2) << kOpcodeShift, 333 JAL = ((0U << 3) + 3) << kOpcodeShift, 334 BEQ = ((0U << 3) + 4) << kOpcodeShift, 335 BNE = ((0U << 3) + 5) << kOpcodeShift, 336 BLEZ = ((0U << 3) + 6) << kOpcodeShift, 337 BGTZ = ((0U << 3) + 7) << kOpcodeShift, 338 339 ADDI = ((1U << 3) + 0) << kOpcodeShift, 340 ADDIU = ((1U << 3) + 1) << kOpcodeShift, 341 SLTI = ((1U << 3) + 2) << kOpcodeShift, 342 SLTIU = ((1U << 3) + 3) << kOpcodeShift, 343 ANDI = ((1U << 3) + 4) << kOpcodeShift, 344 ORI = ((1U << 3) + 5) << kOpcodeShift, 345 XORI = ((1U << 3) + 6) << kOpcodeShift, 346 LUI = ((1U << 3) + 7) << kOpcodeShift, // LUI/AUI family. 347 348 BEQC = ((2U << 3) + 0) << kOpcodeShift, 349 COP1 = ((2U << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. 350 BEQL = ((2U << 3) + 4) << kOpcodeShift, 351 BNEL = ((2U << 3) + 5) << kOpcodeShift, 352 BLEZL = ((2U << 3) + 6) << kOpcodeShift, 353 BGTZL = ((2U << 3) + 7) << kOpcodeShift, 354 355 DADDI = ((3U << 3) + 0) << kOpcodeShift, // This is also BNEC. 356 SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift, 357 SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift, 358 359 LB = ((4U << 3) + 0) << kOpcodeShift, 360 LH = ((4U << 3) + 1) << kOpcodeShift, 361 LWL = ((4U << 3) + 2) << kOpcodeShift, 362 LW = ((4U << 3) + 3) << kOpcodeShift, 363 LBU = ((4U << 3) + 4) << kOpcodeShift, 364 LHU = ((4U << 3) + 5) << kOpcodeShift, 365 LWR = ((4U << 3) + 6) << kOpcodeShift, 366 SB = ((5U << 3) + 0) << kOpcodeShift, 367 SH = ((5U << 3) + 1) << kOpcodeShift, 368 SWL = ((5U << 3) + 2) << kOpcodeShift, 369 SW = ((5U << 3) + 3) << kOpcodeShift, 370 SWR = ((5U << 3) + 6) << kOpcodeShift, 371 372 LWC1 = ((6U << 3) + 1) << kOpcodeShift, 373 BC = ((6U << 3) + 2) << kOpcodeShift, 374 LDC1 = ((6U << 3) + 5) << kOpcodeShift, 375 POP66 = ((6U << 3) + 6) << kOpcodeShift, // beqzc, jic 376 377 PREF = ((6U << 3) + 3) << kOpcodeShift, 378 379 SWC1 = ((7U << 3) + 1) << kOpcodeShift, 380 BALC = ((7U << 3) + 2) << kOpcodeShift, 381 PCREL = ((7U << 3) + 3) << kOpcodeShift, 382 SDC1 = ((7U << 3) + 5) << kOpcodeShift, 383 POP76 = ((7U << 3) + 6) << kOpcodeShift, // bnezc, jialc 384 385 COP1X = ((1U << 4) + 3) << kOpcodeShift, 386 387 // New r6 instruction. 388 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc 389 POP07 = BGTZ, // bltuc/bgtuc, bgtzalc, bltzalc 390 POP10 = ADDI, // beqzalc, bovc, beqc 391 POP26 = BLEZL, // bgezc, blezc, bgec/blec 392 POP27 = BGTZL, // bgtzc, bltzc, bltc/bgtc 393 POP30 = DADDI, // bnezalc, bvnc, bnec 394 }; 395 396 enum SecondaryField : uint32_t { 397 // SPECIAL Encoding of Function Field. 398 SLL = ((0U << 3) + 0), 399 MOVCI = ((0U << 3) + 1), 400 SRL = ((0U << 3) + 2), 401 SRA = ((0U << 3) + 3), 402 SLLV = ((0U << 3) + 4), 403 LSA = ((0U << 3) + 5), 404 SRLV = ((0U << 3) + 6), 405 SRAV = ((0U << 3) + 7), 406 407 JR = ((1U << 3) + 0), 408 JALR = ((1U << 3) + 1), 409 MOVZ = ((1U << 3) + 2), 410 MOVN = ((1U << 3) + 3), 411 BREAK = ((1U << 3) + 5), 412 413 MFHI = ((2U << 3) + 0), 414 CLZ_R6 = ((2U << 3) + 0), 415 CLO_R6 = ((2U << 3) + 1), 416 MFLO = ((2U << 3) + 2), 417 418 MULT = ((3U << 3) + 0), 419 MULTU = ((3U << 3) + 1), 420 DIV = ((3U << 3) + 2), 421 DIVU = ((3U << 3) + 3), 422 423 ADD = ((4U << 3) + 0), 424 ADDU = ((4U << 3) + 1), 425 SUB = ((4U << 3) + 2), 426 SUBU = ((4U << 3) + 3), 427 AND = ((4U << 3) + 4), 428 OR = ((4U << 3) + 5), 429 XOR = ((4U << 3) + 6), 430 NOR = ((4U << 3) + 7), 431 432 SLT = ((5U << 3) + 2), 433 SLTU = ((5U << 3) + 3), 434 435 TGE = ((6U << 3) + 0), 436 TGEU = ((6U << 3) + 1), 437 TLT = ((6U << 3) + 2), 438 TLTU = ((6U << 3) + 3), 439 TEQ = ((6U << 3) + 4), 440 SELEQZ_S = ((6U << 3) + 5), 441 TNE = ((6U << 3) + 6), 442 SELNEZ_S = ((6U << 3) + 7), 443 444 // Multiply integers in r6. 445 MUL_MUH = ((3U << 3) + 0), // MUL, MUH. 446 MUL_MUH_U = ((3U << 3) + 1), // MUL_U, MUH_U. 447 RINT = ((3U << 3) + 2), 448 449 MUL_OP = ((0U << 3) + 2), 450 MUH_OP = ((0U << 3) + 3), 451 DIV_OP = ((0U << 3) + 2), 452 MOD_OP = ((0U << 3) + 3), 453 454 DIV_MOD = ((3U << 3) + 2), 455 DIV_MOD_U = ((3U << 3) + 3), 456 457 // SPECIAL2 Encoding of Function Field. 458 MUL = ((0U << 3) + 2), 459 CLZ = ((4U << 3) + 0), 460 CLO = ((4U << 3) + 1), 461 462 // SPECIAL3 Encoding of Function Field. 463 EXT = ((0U << 3) + 0), 464 INS = ((0U << 3) + 4), 465 BSHFL = ((4U << 3) + 0), 466 467 // SPECIAL3 Encoding of sa Field. 468 BITSWAP = ((0U << 3) + 0), 469 ALIGN = ((0U << 3) + 2), 470 WSBH = ((0U << 3) + 2), 471 SEB = ((2U << 3) + 0), 472 SEH = ((3U << 3) + 0), 473 474 // REGIMM encoding of rt Field. 475 BLTZ = ((0U << 3) + 0) << 16, 476 BGEZ = ((0U << 3) + 1) << 16, 477 BLTZAL = ((2U << 3) + 0) << 16, 478 BGEZAL = ((2U << 3) + 1) << 16, 479 BGEZALL = ((2U << 3) + 3) << 16, 480 481 // COP1 Encoding of rs Field. 482 MFC1 = ((0U << 3) + 0) << 21, 483 CFC1 = ((0U << 3) + 2) << 21, 484 MFHC1 = ((0U << 3) + 3) << 21, 485 MTC1 = ((0U << 3) + 4) << 21, 486 CTC1 = ((0U << 3) + 6) << 21, 487 MTHC1 = ((0U << 3) + 7) << 21, 488 BC1 = ((1U << 3) + 0) << 21, 489 S = ((2U << 3) + 0) << 21, 490 D = ((2U << 3) + 1) << 21, 491 W = ((2U << 3) + 4) << 21, 492 L = ((2U << 3) + 5) << 21, 493 PS = ((2U << 3) + 6) << 21, 494 // COP1 Encoding of Function Field When rs=S. 495 496 ADD_S = ((0U << 3) + 0), 497 SUB_S = ((0U << 3) + 1), 498 MUL_S = ((0U << 3) + 2), 499 DIV_S = ((0U << 3) + 3), 500 ABS_S = ((0U << 3) + 5), 501 SQRT_S = ((0U << 3) + 4), 502 MOV_S = ((0U << 3) + 6), 503 NEG_S = ((0U << 3) + 7), 504 ROUND_L_S = ((1U << 3) + 0), 505 TRUNC_L_S = ((1U << 3) + 1), 506 CEIL_L_S = ((1U << 3) + 2), 507 FLOOR_L_S = ((1U << 3) + 3), 508 ROUND_W_S = ((1U << 3) + 4), 509 TRUNC_W_S = ((1U << 3) + 5), 510 CEIL_W_S = ((1U << 3) + 6), 511 FLOOR_W_S = ((1U << 3) + 7), 512 RECIP_S = ((2U << 3) + 5), 513 RSQRT_S = ((2U << 3) + 6), 514 CLASS_S = ((3U << 3) + 3), 515 CVT_D_S = ((4U << 3) + 1), 516 CVT_W_S = ((4U << 3) + 4), 517 CVT_L_S = ((4U << 3) + 5), 518 CVT_PS_S = ((4U << 3) + 6), 519 520 // COP1 Encoding of Function Field When rs=D. 521 ADD_D = ((0U << 3) + 0), 522 SUB_D = ((0U << 3) + 1), 523 MUL_D = ((0U << 3) + 2), 524 DIV_D = ((0U << 3) + 3), 525 SQRT_D = ((0U << 3) + 4), 526 ABS_D = ((0U << 3) + 5), 527 MOV_D = ((0U << 3) + 6), 528 NEG_D = ((0U << 3) + 7), 529 ROUND_L_D = ((1U << 3) + 0), 530 TRUNC_L_D = ((1U << 3) + 1), 531 CEIL_L_D = ((1U << 3) + 2), 532 FLOOR_L_D = ((1U << 3) + 3), 533 ROUND_W_D = ((1U << 3) + 4), 534 TRUNC_W_D = ((1U << 3) + 5), 535 CEIL_W_D = ((1U << 3) + 6), 536 FLOOR_W_D = ((1U << 3) + 7), 537 RECIP_D = ((2U << 3) + 5), 538 RSQRT_D = ((2U << 3) + 6), 539 CLASS_D = ((3U << 3) + 3), 540 MIN = ((3U << 3) + 4), 541 MINA = ((3U << 3) + 5), 542 MAX = ((3U << 3) + 6), 543 MAXA = ((3U << 3) + 7), 544 CVT_S_D = ((4U << 3) + 0), 545 CVT_W_D = ((4U << 3) + 4), 546 CVT_L_D = ((4U << 3) + 5), 547 C_F_D = ((6U << 3) + 0), 548 C_UN_D = ((6U << 3) + 1), 549 C_EQ_D = ((6U << 3) + 2), 550 C_UEQ_D = ((6U << 3) + 3), 551 C_OLT_D = ((6U << 3) + 4), 552 C_ULT_D = ((6U << 3) + 5), 553 C_OLE_D = ((6U << 3) + 6), 554 C_ULE_D = ((6U << 3) + 7), 555 556 // COP1 Encoding of Function Field When rs=W or L. 557 CVT_S_W = ((4U << 3) + 0), 558 CVT_D_W = ((4U << 3) + 1), 559 CVT_S_L = ((4U << 3) + 0), 560 CVT_D_L = ((4U << 3) + 1), 561 BC1EQZ = ((2U << 2) + 1) << 21, 562 BC1NEZ = ((3U << 2) + 1) << 21, 563 // COP1 CMP positive predicates Bit 5..4 = 00. 564 CMP_AF = ((0U << 3) + 0), 565 CMP_UN = ((0U << 3) + 1), 566 CMP_EQ = ((0U << 3) + 2), 567 CMP_UEQ = ((0U << 3) + 3), 568 CMP_LT = ((0U << 3) + 4), 569 CMP_ULT = ((0U << 3) + 5), 570 CMP_LE = ((0U << 3) + 6), 571 CMP_ULE = ((0U << 3) + 7), 572 CMP_SAF = ((1U << 3) + 0), 573 CMP_SUN = ((1U << 3) + 1), 574 CMP_SEQ = ((1U << 3) + 2), 575 CMP_SUEQ = ((1U << 3) + 3), 576 CMP_SSLT = ((1U << 3) + 4), 577 CMP_SSULT = ((1U << 3) + 5), 578 CMP_SLE = ((1U << 3) + 6), 579 CMP_SULE = ((1U << 3) + 7), 580 // COP1 CMP negative predicates Bit 5..4 = 01. 581 CMP_AT = ((2U << 3) + 0), // Reserved, not implemented. 582 CMP_OR = ((2U << 3) + 1), 583 CMP_UNE = ((2U << 3) + 2), 584 CMP_NE = ((2U << 3) + 3), 585 CMP_UGE = ((2U << 3) + 4), // Reserved, not implemented. 586 CMP_OGE = ((2U << 3) + 5), // Reserved, not implemented. 587 CMP_UGT = ((2U << 3) + 6), // Reserved, not implemented. 588 CMP_OGT = ((2U << 3) + 7), // Reserved, not implemented. 589 CMP_SAT = ((3U << 3) + 0), // Reserved, not implemented. 590 CMP_SOR = ((3U << 3) + 1), 591 CMP_SUNE = ((3U << 3) + 2), 592 CMP_SNE = ((3U << 3) + 3), 593 CMP_SUGE = ((3U << 3) + 4), // Reserved, not implemented. 594 CMP_SOGE = ((3U << 3) + 5), // Reserved, not implemented. 595 CMP_SUGT = ((3U << 3) + 6), // Reserved, not implemented. 596 CMP_SOGT = ((3U << 3) + 7), // Reserved, not implemented. 597 598 SEL = ((2U << 3) + 0), 599 MOVZ_C = ((2U << 3) + 2), 600 MOVN_C = ((2U << 3) + 3), 601 SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR registers. 602 MOVF = ((2U << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt 603 SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR registers. 604 // COP1 Encoding of Function Field When rs=PS. 605 // COP1X Encoding of Function Field. 606 MADD_D = ((4U << 3) + 1), 607 608 // PCREL Encoding of rt Field. 609 ADDIUPC = ((0U << 2) + 0), 610 LWPC = ((0U << 2) + 1), 611 AUIPC = ((3U << 3) + 6), 612 ALUIPC = ((3U << 3) + 7), 613 614 // POP66 Encoding of rs Field. 615 JIC = ((0U << 5) + 0), 616 617 // POP76 Encoding of rs Field. 618 JIALC = ((0U << 5) + 0), 619 620 NULLSF = 0U 621 }; 622 623 624 // ----- Emulated conditions. 625 // On MIPS we use this enum to abstract from conditional branch instructions. 626 // The 'U' prefix is used to specify unsigned comparisons. 627 // Opposite conditions must be paired as odd/even numbers 628 // because 'NegateCondition' function flips LSB to negate condition. 629 enum Condition { 630 // Any value < 0 is considered no_condition. 631 kNoCondition = -1, 632 overflow = 0, 633 no_overflow = 1, 634 Uless = 2, 635 Ugreater_equal = 3, 636 Uless_equal = 4, 637 Ugreater = 5, 638 equal = 6, 639 not_equal = 7, // Unordered or Not Equal. 640 negative = 8, 641 positive = 9, 642 parity_even = 10, 643 parity_odd = 11, 644 less = 12, 645 greater_equal = 13, 646 less_equal = 14, 647 greater = 15, 648 ueq = 16, // Unordered or Equal. 649 ogl = 17, // Ordered and Not Equal. 650 cc_always = 18, 651 652 // Aliases. 653 carry = Uless, 654 not_carry = Ugreater_equal, 655 zero = equal, 656 eq = equal, 657 not_zero = not_equal, 658 ne = not_equal, 659 nz = not_equal, 660 sign = negative, 661 not_sign = positive, 662 mi = negative, 663 pl = positive, 664 hi = Ugreater, 665 ls = Uless_equal, 666 ge = greater_equal, 667 lt = less, 668 gt = greater, 669 le = less_equal, 670 hs = Ugreater_equal, 671 lo = Uless, 672 al = cc_always, 673 ult = Uless, 674 uge = Ugreater_equal, 675 ule = Uless_equal, 676 ugt = Ugreater, 677 cc_default = kNoCondition 678 }; 679 680 681 // Returns the equivalent of !cc. 682 // Negation of the default kNoCondition (-1) results in a non-default 683 // no_condition value (-2). As long as tests for no_condition check 684 // for condition < 0, this will work as expected. 685 inline Condition NegateCondition(Condition cc) { 686 DCHECK(cc != cc_always); 687 return static_cast<Condition>(cc ^ 1); 688 } 689 690 691 inline Condition NegateFpuCondition(Condition cc) { 692 DCHECK(cc != cc_always); 693 switch (cc) { 694 case ult: 695 return ge; 696 case ugt: 697 return le; 698 case uge: 699 return lt; 700 case ule: 701 return gt; 702 case lt: 703 return uge; 704 case gt: 705 return ule; 706 case ge: 707 return ult; 708 case le: 709 return ugt; 710 case eq: 711 return ne; 712 case ne: 713 return eq; 714 case ueq: 715 return ogl; 716 case ogl: 717 return ueq; 718 default: 719 return cc; 720 } 721 } 722 723 724 // Commute a condition such that {a cond b == b cond' a}. 725 inline Condition CommuteCondition(Condition cc) { 726 switch (cc) { 727 case Uless: 728 return Ugreater; 729 case Ugreater: 730 return Uless; 731 case Ugreater_equal: 732 return Uless_equal; 733 case Uless_equal: 734 return Ugreater_equal; 735 case less: 736 return greater; 737 case greater: 738 return less; 739 case greater_equal: 740 return less_equal; 741 case less_equal: 742 return greater_equal; 743 default: 744 return cc; 745 } 746 } 747 748 749 // ----- Coprocessor conditions. 750 enum FPUCondition { 751 kNoFPUCondition = -1, 752 753 F = 0x00, // False. 754 UN = 0x01, // Unordered. 755 EQ = 0x02, // Equal. 756 UEQ = 0x03, // Unordered or Equal. 757 OLT = 0x04, // Ordered or Less Than, on Mips release < 6. 758 LT = 0x04, // Ordered or Less Than, on Mips release >= 6. 759 ULT = 0x05, // Unordered or Less Than. 760 OLE = 0x06, // Ordered or Less Than or Equal, on Mips release < 6. 761 LE = 0x06, // Ordered or Less Than or Equal, on Mips release >= 6. 762 ULE = 0x07, // Unordered or Less Than or Equal. 763 764 // Following constants are available on Mips release >= 6 only. 765 ORD = 0x11, // Ordered, on Mips release >= 6. 766 UNE = 0x12, // Not equal, on Mips release >= 6. 767 NE = 0x13, // Ordered Greater Than or Less Than. on Mips >= 6 only. 768 }; 769 770 771 // FPU rounding modes. 772 enum FPURoundingMode { 773 RN = 0 << 0, // Round to Nearest. 774 RZ = 1 << 0, // Round towards zero. 775 RP = 2 << 0, // Round towards Plus Infinity. 776 RM = 3 << 0, // Round towards Minus Infinity. 777 778 // Aliases. 779 kRoundToNearest = RN, 780 kRoundToZero = RZ, 781 kRoundToPlusInf = RP, 782 kRoundToMinusInf = RM, 783 784 mode_round = RN, 785 mode_ceil = RP, 786 mode_floor = RM, 787 mode_trunc = RZ 788 }; 789 790 const uint32_t kFPURoundingModeMask = 3 << 0; 791 792 enum CheckForInexactConversion { 793 kCheckForInexactConversion, 794 kDontCheckForInexactConversion 795 }; 796 797 798 // ----------------------------------------------------------------------------- 799 // Hints. 800 801 // Branch hints are not used on the MIPS. They are defined so that they can 802 // appear in shared function signatures, but will be ignored in MIPS 803 // implementations. 804 enum Hint { 805 no_hint = 0 806 }; 807 808 809 inline Hint NegateHint(Hint hint) { 810 return no_hint; 811 } 812 813 814 // ----------------------------------------------------------------------------- 815 // Specific instructions, constants, and masks. 816 // These constants are declared in assembler-mips.cc, as they use named 817 // registers and other constants. 818 819 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 820 // operations as post-increment of sp. 821 extern const Instr kPopInstruction; 822 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. 823 extern const Instr kPushInstruction; 824 // sw(r, MemOperand(sp, 0)) 825 extern const Instr kPushRegPattern; 826 // lw(r, MemOperand(sp, 0)) 827 extern const Instr kPopRegPattern; 828 extern const Instr kLwRegFpOffsetPattern; 829 extern const Instr kSwRegFpOffsetPattern; 830 extern const Instr kLwRegFpNegOffsetPattern; 831 extern const Instr kSwRegFpNegOffsetPattern; 832 // A mask for the Rt register for push, pop, lw, sw instructions. 833 extern const Instr kRtMask; 834 extern const Instr kLwSwInstrTypeMask; 835 extern const Instr kLwSwInstrArgumentMask; 836 extern const Instr kLwSwOffsetMask; 837 838 // Break 0xfffff, reserved for redirected real time call. 839 const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6; 840 // A nop instruction. (Encoding of sll 0 0 0). 841 const Instr nopInstr = 0; 842 843 static constexpr uint64_t OpcodeToBitNumber(Opcode opcode) { 844 return 1ULL << (static_cast<uint32_t>(opcode) >> kOpcodeShift); 845 } 846 847 848 class Instruction { 849 public: 850 enum { 851 kInstrSize = 4, 852 kInstrSizeLog2 = 2, 853 // On MIPS PC cannot actually be directly accessed. We behave as if PC was 854 // always the value of the current instruction being executed. 855 kPCReadOffset = 0 856 }; 857 858 // Get the raw instruction bits. 859 inline Instr InstructionBits() const { 860 return *reinterpret_cast<const Instr*>(this); 861 } 862 863 // Set the raw instruction bits to value. 864 inline void SetInstructionBits(Instr value) { 865 *reinterpret_cast<Instr*>(this) = value; 866 } 867 868 // Read one particular bit out of the instruction bits. 869 inline int Bit(int nr) const { 870 return (InstructionBits() >> nr) & 1; 871 } 872 873 // Read a bit field out of the instruction bits. 874 inline int Bits(int hi, int lo) const { 875 return (InstructionBits() >> lo) & ((2U << (hi - lo)) - 1); 876 } 877 878 // Instruction type. 879 enum Type { 880 kRegisterType, 881 kImmediateType, 882 kJumpType, 883 kUnsupported = -1 884 }; 885 886 enum TypeChecks { NORMAL, EXTRA }; 887 888 889 static constexpr uint64_t kOpcodeImmediateTypeMask = 890 OpcodeToBitNumber(REGIMM) | OpcodeToBitNumber(BEQ) | 891 OpcodeToBitNumber(BNE) | OpcodeToBitNumber(BLEZ) | 892 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) | 893 OpcodeToBitNumber(DADDI) | OpcodeToBitNumber(ADDIU) | 894 OpcodeToBitNumber(SLTI) | OpcodeToBitNumber(SLTIU) | 895 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) | 896 OpcodeToBitNumber(XORI) | OpcodeToBitNumber(LUI) | 897 OpcodeToBitNumber(BEQL) | OpcodeToBitNumber(BNEL) | 898 OpcodeToBitNumber(BLEZL) | OpcodeToBitNumber(BGTZL) | 899 OpcodeToBitNumber(POP66) | OpcodeToBitNumber(POP76) | 900 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) | 901 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) | 902 OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) | 903 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) | 904 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) | 905 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) | 906 OpcodeToBitNumber(PCREL) | OpcodeToBitNumber(BC) | 907 OpcodeToBitNumber(BALC); 908 909 #define FunctionFieldToBitNumber(function) (1ULL << function) 910 911 static const uint64_t kFunctionFieldRegisterTypeMask = 912 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) | 913 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) | 914 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) | 915 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(SRLV) | 916 FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(LSA) | 917 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) | 918 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(MULTU) | 919 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DIVU) | 920 FunctionFieldToBitNumber(ADD) | FunctionFieldToBitNumber(ADDU) | 921 FunctionFieldToBitNumber(SUB) | FunctionFieldToBitNumber(SUBU) | 922 FunctionFieldToBitNumber(AND) | FunctionFieldToBitNumber(OR) | 923 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) | 924 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) | 925 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) | 926 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) | 927 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) | 928 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) | 929 FunctionFieldToBitNumber(MOVCI) | FunctionFieldToBitNumber(SELEQZ_S) | 930 FunctionFieldToBitNumber(SELNEZ_S); 931 932 933 // Get the encoding type of the instruction. 934 inline Type InstructionType(TypeChecks checks = NORMAL) const; 935 936 // Accessors for the different named fields used in the MIPS encoding. 937 inline Opcode OpcodeValue() const { 938 return static_cast<Opcode>( 939 Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift)); 940 } 941 942 inline int RsValue() const { 943 DCHECK(InstructionType() == kRegisterType || 944 InstructionType() == kImmediateType); 945 return Bits(kRsShift + kRsBits - 1, kRsShift); 946 } 947 948 inline int RtValue() const { 949 DCHECK(InstructionType() == kRegisterType || 950 InstructionType() == kImmediateType); 951 return Bits(kRtShift + kRtBits - 1, kRtShift); 952 } 953 954 inline int RdValue() const { 955 DCHECK(InstructionType() == kRegisterType); 956 return Bits(kRdShift + kRdBits - 1, kRdShift); 957 } 958 959 inline int SaValue() const { 960 DCHECK(InstructionType() == kRegisterType); 961 return Bits(kSaShift + kSaBits - 1, kSaShift); 962 } 963 964 inline int LsaSaValue() const { 965 DCHECK(InstructionType() == kRegisterType); 966 return Bits(kSaShift + kLsaSaBits - 1, kSaShift); 967 } 968 969 inline int FunctionValue() const { 970 DCHECK(InstructionType() == kRegisterType || 971 InstructionType() == kImmediateType); 972 return Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift); 973 } 974 975 inline int FdValue() const { 976 return Bits(kFdShift + kFdBits - 1, kFdShift); 977 } 978 979 inline int FsValue() const { 980 return Bits(kFsShift + kFsBits - 1, kFsShift); 981 } 982 983 inline int FtValue() const { 984 return Bits(kFtShift + kFtBits - 1, kFtShift); 985 } 986 987 inline int FrValue() const { 988 return Bits(kFrShift + kFrBits -1, kFrShift); 989 } 990 991 inline int Bp2Value() const { 992 DCHECK(InstructionType() == kRegisterType); 993 return Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift); 994 } 995 996 // Float Compare condition code instruction bits. 997 inline int FCccValue() const { 998 return Bits(kFCccShift + kFCccBits - 1, kFCccShift); 999 } 1000 1001 // Float Branch condition code instruction bits. 1002 inline int FBccValue() const { 1003 return Bits(kFBccShift + kFBccBits - 1, kFBccShift); 1004 } 1005 1006 // Float Branch true/false instruction bit. 1007 inline int FBtrueValue() const { 1008 return Bits(kFBtrueShift + kFBtrueBits - 1, kFBtrueShift); 1009 } 1010 1011 // Return the fields at their original place in the instruction encoding. 1012 inline Opcode OpcodeFieldRaw() const { 1013 return static_cast<Opcode>(InstructionBits() & kOpcodeMask); 1014 } 1015 1016 inline int RsFieldRaw() const { 1017 DCHECK(InstructionType() == kRegisterType || 1018 InstructionType() == kImmediateType); 1019 return InstructionBits() & kRsFieldMask; 1020 } 1021 1022 // Same as above function, but safe to call within InstructionType(). 1023 inline int RsFieldRawNoAssert() const { 1024 return InstructionBits() & kRsFieldMask; 1025 } 1026 1027 inline int RtFieldRaw() const { 1028 DCHECK(InstructionType() == kRegisterType || 1029 InstructionType() == kImmediateType); 1030 return InstructionBits() & kRtFieldMask; 1031 } 1032 1033 inline int RdFieldRaw() const { 1034 DCHECK(InstructionType() == kRegisterType); 1035 return InstructionBits() & kRdFieldMask; 1036 } 1037 1038 inline int SaFieldRaw() const { 1039 return InstructionBits() & kSaFieldMask; 1040 } 1041 1042 inline int FunctionFieldRaw() const { 1043 return InstructionBits() & kFunctionFieldMask; 1044 } 1045 1046 // Get the secondary field according to the opcode. 1047 inline int SecondaryValue() const { 1048 Opcode op = OpcodeFieldRaw(); 1049 switch (op) { 1050 case SPECIAL: 1051 case SPECIAL2: 1052 return FunctionValue(); 1053 case COP1: 1054 return RsValue(); 1055 case REGIMM: 1056 return RtValue(); 1057 default: 1058 return NULLSF; 1059 } 1060 } 1061 1062 inline int32_t ImmValue(int bits) const { 1063 DCHECK(InstructionType() == kImmediateType); 1064 return Bits(bits - 1, 0); 1065 } 1066 1067 inline int32_t Imm16Value() const { 1068 DCHECK(InstructionType() == kImmediateType); 1069 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift); 1070 } 1071 1072 inline int32_t Imm18Value() const { 1073 DCHECK(InstructionType() == kImmediateType); 1074 return Bits(kImm18Shift + kImm18Bits - 1, kImm18Shift); 1075 } 1076 1077 inline int32_t Imm19Value() const { 1078 DCHECK(InstructionType() == kImmediateType); 1079 return Bits(kImm19Shift + kImm19Bits - 1, kImm19Shift); 1080 } 1081 1082 inline int32_t Imm21Value() const { 1083 DCHECK(InstructionType() == kImmediateType); 1084 return Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift); 1085 } 1086 1087 inline int32_t Imm26Value() const { 1088 DCHECK((InstructionType() == kJumpType) || 1089 (InstructionType() == kImmediateType)); 1090 return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); 1091 } 1092 1093 static bool IsForbiddenAfterBranchInstr(Instr instr); 1094 1095 // Say if the instruction should not be used in a branch delay slot or 1096 // immediately after a compact branch. 1097 inline bool IsForbiddenAfterBranch() const { 1098 return IsForbiddenAfterBranchInstr(InstructionBits()); 1099 } 1100 1101 inline bool IsForbiddenInBranchDelay() const { 1102 return IsForbiddenAfterBranch(); 1103 } 1104 1105 // Say if the instruction 'links'. e.g. jal, bal. 1106 bool IsLinkingInstruction() const; 1107 // Say if the instruction is a break or a trap. 1108 bool IsTrap() const; 1109 1110 // Instructions are read of out a code stream. The only way to get a 1111 // reference to an instruction is to convert a pointer. There is no way 1112 // to allocate or create instances of class Instruction. 1113 // Use the At(pc) function to create references to Instruction. 1114 static Instruction* At(byte* pc) { 1115 return reinterpret_cast<Instruction*>(pc); 1116 } 1117 1118 private: 1119 // We need to prevent the creation of instances of class Instruction. 1120 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 1121 }; 1122 1123 1124 // ----------------------------------------------------------------------------- 1125 // MIPS assembly various constants. 1126 1127 // C/C++ argument slots size. 1128 const int kCArgSlotCount = 4; 1129 const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize; 1130 const int kInvalidStackOffset = -1; 1131 // JS argument slots size. 1132 const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize; 1133 // Assembly builtins argument slots size. 1134 const int kBArgsSlotsSize = 0 * Instruction::kInstrSize; 1135 1136 const int kBranchReturnOffset = 2 * Instruction::kInstrSize; 1137 1138 1139 Instruction::Type Instruction::InstructionType(TypeChecks checks) const { 1140 if (checks == EXTRA) { 1141 if (OpcodeToBitNumber(OpcodeFieldRaw()) & kOpcodeImmediateTypeMask) { 1142 return kImmediateType; 1143 } 1144 } 1145 switch (OpcodeFieldRaw()) { 1146 case SPECIAL: 1147 if (checks == EXTRA) { 1148 if (FunctionFieldToBitNumber(FunctionFieldRaw()) & 1149 kFunctionFieldRegisterTypeMask) { 1150 return kRegisterType; 1151 } else { 1152 return kUnsupported; 1153 } 1154 } else { 1155 return kRegisterType; 1156 } 1157 break; 1158 case SPECIAL2: 1159 switch (FunctionFieldRaw()) { 1160 case MUL: 1161 case CLZ: 1162 return kRegisterType; 1163 default: 1164 return kUnsupported; 1165 } 1166 break; 1167 case SPECIAL3: 1168 switch (FunctionFieldRaw()) { 1169 case INS: 1170 case EXT: 1171 return kRegisterType; 1172 case BSHFL: { 1173 int sa = SaFieldRaw() >> kSaShift; 1174 switch (sa) { 1175 case BITSWAP: 1176 return kRegisterType; 1177 case WSBH: 1178 case SEB: 1179 case SEH: 1180 return kUnsupported; 1181 } 1182 sa >>= kBp2Bits; 1183 switch (sa) { 1184 case ALIGN: 1185 return kRegisterType; 1186 default: 1187 return kUnsupported; 1188 } 1189 } 1190 default: 1191 return kUnsupported; 1192 } 1193 break; 1194 case COP1: // Coprocessor instructions. 1195 switch (RsFieldRawNoAssert()) { 1196 case BC1: // Branch on coprocessor condition. 1197 case BC1EQZ: 1198 case BC1NEZ: 1199 return kImmediateType; 1200 default: 1201 return kRegisterType; 1202 } 1203 break; 1204 case COP1X: 1205 return kRegisterType; 1206 1207 // 26 bits immediate type instructions. e.g.: j imm26. 1208 case J: 1209 case JAL: 1210 return kJumpType; 1211 1212 default: 1213 if (checks == NORMAL) { 1214 return kImmediateType; 1215 } else { 1216 return kUnsupported; 1217 } 1218 } 1219 } 1220 1221 #undef OpcodeToBitNumber 1222 #undef FunctionFieldToBitNumber 1223 } // namespace internal 1224 } // namespace v8 1225 1226 #endif // #ifndef V8_MIPS_CONSTANTS_H_ 1227
