| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
56 // A single ADDiu will do if RemSize <= 16.
58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
80 // Replace a ADDiu & SLL pair with a LUi.
82 // ADDiu 0x0111
87 // Check if the first two instructions are ADDiu and SLL and the shift amount
89 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
93 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
131 ADDiu = Mips::ADDiu
[all...] |
| MipsAnalyzeImmediate.h | 26 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
35 /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi;
|
| MipsLongBranch.cpp | 280 // addiu $sp, $sp, -8
284 // addiu $at, $at, %lo($tgt - $baltgt)
289 // addiu $sp, $sp, 8
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
300 // LUi and ADDiu instructions create 32-bit offset of the target basic
309 // we replace LUi and ADDiu with pseudo instructions
312 // instructions to LUi and ADDiu in the MC layer, we will create
335 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
339 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
445 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0
[all...] |
| MipsMCInstLower.cpp | 209 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu,
|
| MipsSEISelDAGToDAG.cpp | 90 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91 if ((MI.getOpcode() == Mips::ADDiu) &&
169 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
183 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
188 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
199 // 1. addiu $2, $2, %lo(_gp_disp)
210 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
345 // addiu $2, $2, %lo($CPI1_0)
778 // instructions (ADDiu, ORI and SLL) in that it does not have a registe
[all...] |
| MipsSEInstrInfo.cpp | 433 unsigned ADDiu = ABI.GetPtrAddiuOp();
439 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
469 // instructions (ADDiu, ORI and SLL) in that it does not have a register
|
| MipsFastISel.cpp | 308 unsigned Opc = Mips::ADDiu;
367 emitInst(Mips::ADDiu, TempReg)
690 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
691 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
[all...] |
| MipsSEFrameLowering.cpp | 394 unsigned ADDiu = ABI.GetPtrAddiuOp();
516 // addiu $Reg, $zero, -MaxAlignment
523 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| MipsISelLowering.cpp | 640 // addiu $reg2, $reg1, y-1
647 // addiu $reg2, $reg1, y-1
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsABIInfo.cpp | 118 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
|
| MipsTargetStreamer.cpp | 753 // addiu $gp, $gp, %lo(__gnu_local_gp)
770 TmpInst.setOpcode(Mips::ADDiu);
847 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
848 Inst.setOpcode(Mips::ADDiu);
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
