| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 68 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
69 DBG_VALUE = 11,
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| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 217 case TargetOpcode::DBG_VALUE:
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| LiveDebugVariables.cpp | 12 // Remove all DBG_VALUE instructions referencing virtual registers and replace
17 // are moved between registers and stack slots. Finally emit new DBG_VALUE
101 /// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
131 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
217 // A later DBG_VALUE at the same SlotIndex overrides the old location.
266 /// emitDebugValues - Recreate DBG_VALUE instruction from data structures.
310 /// handleDebugValue - Add DBG_VALUE instruction to our maps.
311 /// @param MI DBG_VALUE instruction
313 /// @return True if the DBG_VALUE instruction should be deleted.
316 /// collectDebugValues - Collect and erase all DBG_VALUE instructions, addin
[all...] |
| RegAllocFast.cpp | 293 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
308 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
317 // Now this register is spilled there is should not be any DBG_VALUE
864 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
868 // Modify DBG_VALUE now that the value is in a spill slot
[all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 244 /// this DBG_VALUE instruction.
246 assert(isDebugValue() && "not a DBG_VALUE");
251 /// this DBG_VALUE instruction.
253 assert(isDebugValue() && "not a DBG_VALUE");
733 /// For all definitions mark their uses in DBG_VALUE nodes
755 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
756 /// A DBG_VALUE is indirect iff the first operand is a register and
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 144 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
378 MII->getOpcode() == AArch64::DBG_VALUE ||
454 case AArch64::DBG_VALUE: {
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| AArch64InstrInfo.cpp | 50 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 304 case TargetOpcode::DBG_VALUE:
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| /external/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 272 case XCore::DBG_VALUE:
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 578 if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
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| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 263 case TargetOpcode::DBG_VALUE:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 646 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
661 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
668 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAGISel.cpp | 521 // Insert DBG_VALUE instructions for function arguments to the entry block.
555 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
559 // that COPY instructions also need DBG_VALUE, if it is the only
577 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 844 assert(OpC != PPC::DBG_VALUE &&
[all...] |
| PPCAsmPrinter.cpp | 343 MII->getOpcode() == PPC::DBG_VALUE ||
501 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | [all...] |
| X86FrameLowering.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 691 /// of DBG_VALUE, returning true if it was able to do so. A false return
884 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | [all...] |
