1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright (C) 1993-2014 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #ifndef _MIPS_H_ 24 #define _MIPS_H_ 25 26 #include "bfd.h" 27 28 /* These are bit masks and shift counts to use to access the various 29 fields of an instruction. To retrieve the X field of an 30 instruction, use the expression 31 (i >> OP_SH_X) & OP_MASK_X 32 To set the same field (to j), use 33 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 34 35 Make sure you use fields that are appropriate for the instruction, 36 of course. 37 38 The 'i' format uses OP, RS, RT and IMMEDIATE. 39 40 The 'j' format uses OP and TARGET. 41 42 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 43 44 The 'b' format uses OP, RS, RT and DELTA. 45 46 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 47 48 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 49 50 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 51 breakpoint instruction are not defined; Kane says the breakpoint 52 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 53 only use ten bits). An optional two-operand form of break/sdbbp 54 allows the lower ten bits to be set too, and MIPS32 and later 55 architectures allow 20 bits to be set with a signal operand 56 (using CODE20). 57 58 The syscall instruction uses CODE20. 59 60 The general coprocessor instructions use COPZ. */ 61 62 #define OP_MASK_OP 0x3f 63 #define OP_SH_OP 26 64 #define OP_MASK_RS 0x1f 65 #define OP_SH_RS 21 66 #define OP_MASK_FR 0x1f 67 #define OP_SH_FR 21 68 #define OP_MASK_FMT 0x1f 69 #define OP_SH_FMT 21 70 #define OP_MASK_BCC 0x7 71 #define OP_SH_BCC 18 72 #define OP_MASK_CODE 0x3ff 73 #define OP_SH_CODE 16 74 #define OP_MASK_CODE2 0x3ff 75 #define OP_SH_CODE2 6 76 #define OP_MASK_RT 0x1f 77 #define OP_SH_RT 16 78 #define OP_MASK_FT 0x1f 79 #define OP_SH_FT 16 80 #define OP_MASK_CACHE 0x1f 81 #define OP_SH_CACHE 16 82 #define OP_MASK_RD 0x1f 83 #define OP_SH_RD 11 84 #define OP_MASK_FS 0x1f 85 #define OP_SH_FS 11 86 #define OP_MASK_PREFX 0x1f 87 #define OP_SH_PREFX 11 88 #define OP_MASK_CCC 0x7 89 #define OP_SH_CCC 8 90 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 91 #define OP_SH_CODE20 6 92 #define OP_MASK_SHAMT 0x1f 93 #define OP_SH_SHAMT 6 94 #define OP_MASK_EXTLSB OP_MASK_SHAMT 95 #define OP_SH_EXTLSB OP_SH_SHAMT 96 #define OP_MASK_STYPE OP_MASK_SHAMT 97 #define OP_SH_STYPE OP_SH_SHAMT 98 #define OP_MASK_FD 0x1f 99 #define OP_SH_FD 6 100 #define OP_MASK_TARGET 0x3ffffff 101 #define OP_SH_TARGET 0 102 #define OP_MASK_COPZ 0x1ffffff 103 #define OP_SH_COPZ 0 104 #define OP_MASK_IMMEDIATE 0xffff 105 #define OP_SH_IMMEDIATE 0 106 #define OP_MASK_DELTA 0xffff 107 #define OP_SH_DELTA 0 108 #define OP_MASK_FUNCT 0x3f 109 #define OP_SH_FUNCT 0 110 #define OP_MASK_SPEC 0x3f 111 #define OP_SH_SPEC 0 112 #define OP_SH_LOCC 8 /* FP condition code. */ 113 #define OP_SH_HICC 18 /* FP condition code. */ 114 #define OP_MASK_CC 0x7 115 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 116 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 117 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 118 #define OP_MASK_COP1SPEC 0xf 119 #define OP_MASK_COP1SCLR 0x4 120 #define OP_MASK_COP1CMP 0x3 121 #define OP_SH_COP1CMP 4 122 #define OP_SH_FORMAT 21 /* FP short format field. */ 123 #define OP_MASK_FORMAT 0x7 124 #define OP_SH_TRUE 16 125 #define OP_MASK_TRUE 0x1 126 #define OP_SH_GE 17 127 #define OP_MASK_GE 0x01 128 #define OP_SH_UNSIGNED 16 129 #define OP_MASK_UNSIGNED 0x1 130 #define OP_SH_HINT 16 131 #define OP_MASK_HINT 0x1f 132 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 133 #define OP_MASK_MMI 0x3f 134 #define OP_SH_MMISUB 6 135 #define OP_MASK_MMISUB 0x1f 136 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 137 #define OP_SH_PERFREG 1 138 #define OP_SH_SEL 0 /* Coprocessor select field. */ 139 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 140 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 141 #define OP_MASK_CODE19 0x7ffff 142 #define OP_SH_ALN 21 143 #define OP_MASK_ALN 0x7 144 #define OP_SH_VSEL 21 145 #define OP_MASK_VSEL 0x1f 146 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 147 but 0x8-0xf don't select bytes. */ 148 #define OP_SH_VECBYTE 22 149 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 150 #define OP_SH_VECALIGN 21 151 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 152 #define OP_SH_INSMSB 11 153 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 154 #define OP_SH_EXTMSBD 11 155 156 /* MIPS DSP ASE */ 157 #define OP_SH_DSPACC 11 158 #define OP_MASK_DSPACC 0x3 159 #define OP_SH_DSPACC_S 21 160 #define OP_MASK_DSPACC_S 0x3 161 #define OP_SH_DSPSFT 20 162 #define OP_MASK_DSPSFT 0x3f 163 #define OP_SH_DSPSFT_7 19 164 #define OP_MASK_DSPSFT_7 0x7f 165 #define OP_SH_SA3 21 166 #define OP_MASK_SA3 0x7 167 #define OP_SH_SA4 21 168 #define OP_MASK_SA4 0xf 169 #define OP_SH_IMM8 16 170 #define OP_MASK_IMM8 0xff 171 #define OP_SH_IMM10 16 172 #define OP_MASK_IMM10 0x3ff 173 #define OP_SH_WRDSP 11 174 #define OP_MASK_WRDSP 0x3f 175 #define OP_SH_RDDSP 16 176 #define OP_MASK_RDDSP 0x3f 177 #define OP_SH_BP 11 178 #define OP_MASK_BP 0x3 179 180 /* MIPS MT ASE */ 181 #define OP_SH_MT_U 5 182 #define OP_MASK_MT_U 0x1 183 #define OP_SH_MT_H 4 184 #define OP_MASK_MT_H 0x1 185 #define OP_SH_MTACC_T 18 186 #define OP_MASK_MTACC_T 0x3 187 #define OP_SH_MTACC_D 13 188 #define OP_MASK_MTACC_D 0x3 189 190 /* MIPS MCU ASE */ 191 #define OP_MASK_3BITPOS 0x7 192 #define OP_SH_3BITPOS 12 193 #define OP_MASK_OFFSET12 0xfff 194 #define OP_SH_OFFSET12 0 195 196 #define OP_OP_COP0 0x10 197 #define OP_OP_COP1 0x11 198 #define OP_OP_COP2 0x12 199 #define OP_OP_COP3 0x13 200 #define OP_OP_LWC1 0x31 201 #define OP_OP_LWC2 0x32 202 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 203 #define OP_OP_LDC1 0x35 204 #define OP_OP_LDC2 0x36 205 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 206 #define OP_OP_SWC1 0x39 207 #define OP_OP_SWC2 0x3a 208 #define OP_OP_SWC3 0x3b 209 #define OP_OP_SDC1 0x3d 210 #define OP_OP_SDC2 0x3e 211 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 212 213 /* MIPS VIRT ASE */ 214 #define OP_MASK_CODE10 0x3ff 215 #define OP_SH_CODE10 11 216 217 /* Values in the 'VSEL' field. */ 218 #define MDMX_FMTSEL_IMM_QH 0x1d 219 #define MDMX_FMTSEL_IMM_OB 0x1e 220 #define MDMX_FMTSEL_VEC_QH 0x15 221 #define MDMX_FMTSEL_VEC_OB 0x16 222 223 /* UDI */ 224 #define OP_SH_UDI1 6 225 #define OP_MASK_UDI1 0x1f 226 #define OP_SH_UDI2 6 227 #define OP_MASK_UDI2 0x3ff 228 #define OP_SH_UDI3 6 229 #define OP_MASK_UDI3 0x7fff 230 #define OP_SH_UDI4 6 231 #define OP_MASK_UDI4 0xfffff 232 233 /* Octeon */ 234 #define OP_SH_BBITIND 16 235 #define OP_MASK_BBITIND 0x1f 236 #define OP_SH_CINSPOS 6 237 #define OP_MASK_CINSPOS 0x1f 238 #define OP_SH_CINSLM1 11 239 #define OP_MASK_CINSLM1 0x1f 240 #define OP_SH_SEQI 6 241 #define OP_MASK_SEQI 0x3ff 242 243 /* Loongson */ 244 #define OP_SH_OFFSET_A 6 245 #define OP_MASK_OFFSET_A 0xff 246 #define OP_SH_OFFSET_B 3 247 #define OP_MASK_OFFSET_B 0xff 248 #define OP_SH_OFFSET_C 6 249 #define OP_MASK_OFFSET_C 0x1ff 250 #define OP_SH_RZ 0 251 #define OP_MASK_RZ 0x1f 252 #define OP_SH_FZ 0 253 #define OP_MASK_FZ 0x1f 254 255 /* Every MICROMIPSOP_X definition requires a corresponding OP_X 256 definition, and vice versa. This simplifies various parts 257 of the operand handling in GAS. The fields below only exist 258 in the microMIPS encoding, so define each one to have an empty 259 range. */ 260 #define OP_MASK_TRAP 0 261 #define OP_SH_TRAP 0 262 #define OP_MASK_OFFSET10 0 263 #define OP_SH_OFFSET10 0 264 #define OP_MASK_RS3 0 265 #define OP_SH_RS3 0 266 #define OP_MASK_MB 0 267 #define OP_SH_MB 0 268 #define OP_MASK_MC 0 269 #define OP_SH_MC 0 270 #define OP_MASK_MD 0 271 #define OP_SH_MD 0 272 #define OP_MASK_ME 0 273 #define OP_SH_ME 0 274 #define OP_MASK_MF 0 275 #define OP_SH_MF 0 276 #define OP_MASK_MG 0 277 #define OP_SH_MG 0 278 #define OP_MASK_MH 0 279 #define OP_SH_MH 0 280 #define OP_MASK_MJ 0 281 #define OP_SH_MJ 0 282 #define OP_MASK_ML 0 283 #define OP_SH_ML 0 284 #define OP_MASK_MM 0 285 #define OP_SH_MM 0 286 #define OP_MASK_MN 0 287 #define OP_SH_MN 0 288 #define OP_MASK_MP 0 289 #define OP_SH_MP 0 290 #define OP_MASK_MQ 0 291 #define OP_SH_MQ 0 292 #define OP_MASK_IMMA 0 293 #define OP_SH_IMMA 0 294 #define OP_MASK_IMMB 0 295 #define OP_SH_IMMB 0 296 #define OP_MASK_IMMC 0 297 #define OP_SH_IMMC 0 298 #define OP_MASK_IMMF 0 299 #define OP_SH_IMMF 0 300 #define OP_MASK_IMMG 0 301 #define OP_SH_IMMG 0 302 #define OP_MASK_IMMH 0 303 #define OP_SH_IMMH 0 304 #define OP_MASK_IMMI 0 305 #define OP_SH_IMMI 0 306 #define OP_MASK_IMMJ 0 307 #define OP_SH_IMMJ 0 308 #define OP_MASK_IMML 0 309 #define OP_SH_IMML 0 310 #define OP_MASK_IMMM 0 311 #define OP_SH_IMMM 0 312 #define OP_MASK_IMMN 0 313 #define OP_SH_IMMN 0 314 #define OP_MASK_IMMO 0 315 #define OP_SH_IMMO 0 316 #define OP_MASK_IMMP 0 317 #define OP_SH_IMMP 0 318 #define OP_MASK_IMMQ 0 319 #define OP_SH_IMMQ 0 320 #define OP_MASK_IMMU 0 321 #define OP_SH_IMMU 0 322 #define OP_MASK_IMMW 0 323 #define OP_SH_IMMW 0 324 #define OP_MASK_IMMX 0 325 #define OP_SH_IMMX 0 326 #define OP_MASK_IMMY 0 327 #define OP_SH_IMMY 0 328 329 /* Enhanced VA Scheme */ 330 #define OP_SH_EVAOFFSET 7 331 #define OP_MASK_EVAOFFSET 0x1ff 332 333 /* Enumerates the various types of MIPS operand. */ 334 enum mips_operand_type { 335 /* Described by mips_int_operand. */ 336 OP_INT, 337 338 /* Described by mips_mapped_int_operand. */ 339 OP_MAPPED_INT, 340 341 /* Described by mips_msb_operand. */ 342 OP_MSB, 343 344 /* Described by mips_reg_operand. */ 345 OP_REG, 346 347 /* Like OP_REG, but can be omitted if the register is the same as the 348 previous operand. */ 349 OP_OPTIONAL_REG, 350 351 /* Described by mips_reg_pair_operand. */ 352 OP_REG_PAIR, 353 354 /* Described by mips_pcrel_operand. */ 355 OP_PCREL, 356 357 /* A performance register. The field is 5 bits in size, but the supported 358 values are much more restricted. */ 359 OP_PERF_REG, 360 361 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts 362 as a normal 9-bit signed offset that is multiplied by four, but there 363 are four special cases: 364 365 -2 * 4 => -258 * 4 366 -1 * 4 => -257 * 4 367 0 * 4 => 256 * 4 368 1 * 4 => 257 * 4. */ 369 OP_ADDIUSP_INT, 370 371 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two 372 5-bit register fields, both of which must be set to the destination 373 register. */ 374 OP_CLO_CLZ_DEST, 375 376 /* A register list for a microMIPS LWM or SWM instruction. The operand 377 size determines whether the 16-bit or 32-bit encoding is required. */ 378 OP_LWM_SWM_LIST, 379 380 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ 381 OP_ENTRY_EXIT_LIST, 382 383 /* The register list and frame size for a MIPS16 SAVE or RESTORE 384 instruction. */ 385 OP_SAVE_RESTORE_LIST, 386 387 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: 388 389 V Meaning 390 ----- ------- 391 0EEE0 8 copies of $vN[E], OB format 392 0EE01 4 copies of $vN[E], QH format 393 10110 all 8 elements of $vN, OB format 394 10101 all 4 elements of $vN, QH format 395 11110 8 copies of immediate N, OB format 396 11101 4 copies of immediate N, QH format. */ 397 OP_MDMX_IMM_REG, 398 399 /* A register operand that must match the destination register. */ 400 OP_REPEAT_DEST_REG, 401 402 /* A register operand that must match the previous register. */ 403 OP_REPEAT_PREV_REG, 404 405 /* $pc, which has no encoding in the architectural instruction. */ 406 OP_PC, 407 408 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines 409 which. */ 410 OP_VU0_SUFFIX, 411 412 /* Like OP_VU0_SUFFIX, but used when the operand's value has already 413 been set. Any suffix used here must match the previous value. */ 414 OP_VU0_MATCH_SUFFIX, 415 416 /* An index selected by an integer, e.g. [1]. */ 417 OP_IMM_INDEX, 418 419 /* An index selected by a register, e.g. [$2]. */ 420 OP_REG_INDEX, 421 422 /* The operand spans two 5-bit register fields, both of which must be set to 423 the source register. */ 424 OP_SAME_RS_RT, 425 426 /* Described by mips_prev_operand. */ 427 OP_CHECK_PREV, 428 429 /* A register operand that must not be zero. */ 430 OP_NON_ZERO_REG, 431 432 OP_MAPPED_STRING, 433 OP_MXU_STRIDE 434 }; 435 436 /* Enumerates the types of MIPS register. */ 437 enum mips_reg_operand_type { 438 /* General registers $0-$31. Software names like $at can also be used. */ 439 OP_REG_GP, 440 441 /* Floating-point registers $f0-$f31. */ 442 OP_REG_FP, 443 444 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes 445 can also be written $fcc0-$fcc7. */ 446 OP_REG_CCC, 447 448 /* FPRs used in a vector capacity. They can be written $f0-$f31 449 or $v0-$v31, although the latter form is not used for the VR5400 450 vector instructions. */ 451 OP_REG_VEC, 452 453 /* DSP accumulator registers $ac0-$ac3. */ 454 OP_REG_ACC, 455 456 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can 457 also be used in some contexts. */ 458 OP_REG_COPRO, 459 460 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can 461 also be used in some contexts. */ 462 OP_REG_HW, 463 464 /* Floating-point registers $vf0-$vf31. */ 465 OP_REG_VF, 466 467 /* Integer registers $vi0-$vi31. */ 468 OP_REG_VI, 469 470 /* R5900 VU0 registers $I, $Q, $R and $ACC. */ 471 OP_REG_R5900_I, 472 OP_REG_R5900_Q, 473 OP_REG_R5900_R, 474 OP_REG_R5900_ACC, 475 476 /* MSA registers $w0-$w31. */ 477 OP_REG_MSA, 478 479 /* MSA control registers $0-$31. */ 480 OP_REG_MSA_CTRL, 481 482 OP_REG_MXU, 483 484 OP_REG_MXU_GP 485 }; 486 487 /* Base class for all operands. */ 488 struct mips_operand 489 { 490 /* The type of the operand. */ 491 enum mips_operand_type type; 492 493 /* The operand occupies SIZE bits of the instruction, starting at LSB. */ 494 unsigned short size; 495 unsigned short lsb; 496 }; 497 498 /* Describes an integer operand with a regular encoding pattern. */ 499 struct mips_int_operand 500 { 501 struct mips_operand root; 502 503 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. 504 The cyclically previous field value encodes 1 << SHIFT less than that, 505 and so on. E.g. 506 507 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, 508 but 15 encodes -1. 509 510 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is 511 shifted left two places. 512 513 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except 514 that 0 encodes 8. 515 516 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ 517 unsigned int max_val; 518 int bias; 519 unsigned int shift; 520 521 /* True if the operand should be printed as hex rather than decimal. */ 522 bfd_boolean print_hex; 523 }; 524 525 /* Uses a lookup table to describe a small integer operand. */ 526 struct mips_mapped_int_operand 527 { 528 struct mips_operand root; 529 530 /* Maps each encoding value to the integer that it represents. */ 531 const int *int_map; 532 533 /* True if the operand should be printed as hex rather than decimal. */ 534 bfd_boolean print_hex; 535 }; 536 537 struct mips_mapped_string_operand 538 { 539 struct mips_operand root; 540 const char ** strings; 541 int allow_constants; 542 }; 543 /* An operand that encodes the most significant bit position of a bitfield. 544 Given a bitfield that spans bits [MSB, LSB], some operands of this type 545 encode MSB directly while others encode MSB - LSB. Each operand of this 546 type is preceded by an integer operand that specifies LSB. 547 548 The assembly form varies between instructions. For some instructions, 549 such as EXT, the operand is written as the bitfield size. For others, 550 such as EXTS, it is written in raw MSB - LSB form. */ 551 struct mips_msb_operand 552 { 553 struct mips_operand root; 554 555 /* The assembly-level operand encoded by a field value of 0. */ 556 int bias; 557 558 /* True if the operand encodes MSB directly, false if it encodes 559 MSB - LSB. */ 560 bfd_boolean add_lsb; 561 562 /* The maximum value of MSB + 1. */ 563 unsigned int opsize; 564 }; 565 566 /* Describes a single register operand. */ 567 struct mips_reg_operand 568 { 569 struct mips_operand root; 570 571 /* The type of register. */ 572 enum mips_reg_operand_type reg_type; 573 574 /* If nonnull, REG_MAP[N] gives the register associated with encoding N, 575 otherwise the encoding is the same as the register number. */ 576 const unsigned char *reg_map; 577 }; 578 579 /* Describes an operand that which must match a condition based on the 580 previous operand. */ 581 struct mips_check_prev_operand 582 { 583 struct mips_operand root; 584 585 bfd_boolean greater_than_ok; 586 bfd_boolean less_than_ok; 587 bfd_boolean equal_ok; 588 bfd_boolean zero_ok; 589 }; 590 591 /* Describes an operand that encodes a pair of registers. */ 592 struct mips_reg_pair_operand 593 { 594 struct mips_operand root; 595 596 /* The type of register. */ 597 enum mips_reg_operand_type reg_type; 598 599 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ 600 unsigned char *reg1_map; 601 unsigned char *reg2_map; 602 }; 603 604 /* Describes an operand that is calculated relative to a base PC. 605 The base PC is usually the address of the following instruction, 606 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ 607 struct mips_pcrel_operand 608 { 609 /* Encodes the offset. */ 610 struct mips_int_operand root; 611 612 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', 613 which is then added to the offset encoded by ROOT. */ 614 unsigned int align_log2 : 8; 615 616 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then 617 reinstated. This is true for jumps and branches and false for 618 PC-relative data instructions. */ 619 unsigned int include_isa_bit : 1; 620 621 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. 622 This is true for JALX and false otherwise. */ 623 unsigned int flip_isa_bit : 1; 624 }; 625 626 /* Return true if the assembly syntax allows OPERAND to be omitted. */ 627 628 static inline bfd_boolean 629 mips_optional_operand_p (const struct mips_operand *operand) 630 { 631 return (operand->type == OP_OPTIONAL_REG 632 || operand->type == OP_REPEAT_PREV_REG); 633 } 634 635 /* Return a version of INSN in which the field specified by OPERAND 636 has value UVAL. */ 637 638 static inline unsigned int 639 mips_insert_operand (const struct mips_operand *operand, unsigned int insn, 640 unsigned int uval) 641 { 642 unsigned int mask; 643 644 mask = (1 << operand->size) - 1; 645 insn &= ~(mask << operand->lsb); 646 insn |= (uval & mask) << operand->lsb; 647 return insn; 648 } 649 650 /* Extract OPERAND from instruction INSN. */ 651 652 static inline unsigned int 653 mips_extract_operand (const struct mips_operand *operand, unsigned int insn) 654 { 655 return (insn >> operand->lsb) & ((1 << operand->size) - 1); 656 } 657 658 /* UVAL is the value encoded by OPERAND. Return it in signed form. */ 659 660 static inline int 661 mips_signed_operand (const struct mips_operand *operand, unsigned int uval) 662 { 663 unsigned int sign_bit, mask; 664 665 mask = (1 << operand->size) - 1; 666 sign_bit = 1 << (operand->size - 1); 667 return ((uval + sign_bit) & mask) - sign_bit; 668 } 669 670 /* Return the integer that OPERAND encodes as UVAL. */ 671 672 static inline int 673 mips_decode_int_operand (const struct mips_int_operand *operand, 674 unsigned int uval) 675 { 676 uval |= (operand->max_val - uval) & -(1 << operand->root.size); 677 uval += operand->bias; 678 uval <<= operand->shift; 679 return uval; 680 } 681 682 /* Return the maximum value that can be encoded by OPERAND. */ 683 684 static inline int 685 mips_int_operand_max (const struct mips_int_operand *operand) 686 { 687 return (operand->max_val + operand->bias) << operand->shift; 688 } 689 690 /* Return the minimum value that can be encoded by OPERAND. */ 691 692 static inline int 693 mips_int_operand_min (const struct mips_int_operand *operand) 694 { 695 unsigned int mask; 696 697 mask = (1 << operand->root.size) - 1; 698 return mips_int_operand_max (operand) - (mask << operand->shift); 699 } 700 701 /* Return the register that OPERAND encodes as UVAL. */ 702 703 static inline int 704 mips_decode_reg_operand (const struct mips_reg_operand *operand, 705 unsigned int uval) 706 { 707 if (operand->reg_map) 708 uval = operand->reg_map[uval]; 709 return uval; 710 } 711 712 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. 713 Return the address that it encodes. */ 714 715 static inline bfd_vma 716 mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, 717 bfd_vma base_pc, unsigned int uval) 718 { 719 bfd_vma addr; 720 721 addr = base_pc & -(1 << operand->align_log2); 722 addr += mips_decode_int_operand (&operand->root, uval); 723 if (operand->include_isa_bit) 724 addr |= base_pc & 1; 725 if (operand->flip_isa_bit) 726 addr ^= 1; 727 return addr; 728 } 729 730 /* This structure holds information for a particular instruction. */ 731 732 struct mips_opcode 733 { 734 /* The name of the instruction. */ 735 const char *name; 736 /* A string describing the arguments for this instruction. */ 737 const char *args; 738 /* The basic opcode for the instruction. When assembling, this 739 opcode is modified by the arguments to produce the actual opcode 740 that is used. If pinfo is INSN_MACRO, then this is 0. */ 741 unsigned long match; 742 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 743 relevant portions of the opcode when disassembling. If the 744 actual opcode anded with the match field equals the opcode field, 745 then we have found the correct instruction. If pinfo is 746 INSN_MACRO, then this field is the macro identifier. */ 747 unsigned long mask; 748 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 749 of bits describing the instruction, notably any relevant hazard 750 information. */ 751 unsigned long pinfo; 752 /* A collection of additional bits describing the instruction. */ 753 unsigned long pinfo2; 754 /* A collection of bits describing the instruction sets of which this 755 instruction or macro is a member. */ 756 unsigned long membership; 757 /* A collection of bits describing the ASE of which this instruction 758 or macro is a member. */ 759 unsigned long ase; 760 /* A collection of bits describing the instruction sets of which this 761 instruction or macro is not a member. */ 762 unsigned long exclusions; 763 }; 764 765 /* These are the characters which may appear in the args field of an 766 instruction. They appear in the order in which the fields appear 767 when the instruction is used. Commas and parentheses in the args 768 string are ignored when assembling, and written into the output 769 when disassembling. 770 771 Each of these characters corresponds to a mask field defined above. 772 773 "1" 5 bit sync type (OP_*_STYPE) 774 "<" 5 bit shift amount (OP_*_SHAMT) 775 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 776 "a" 26 bit target address (OP_*_TARGET) 777 "+i" likewise, but flips bit 0 778 "b" 5 bit base register (OP_*_RS) 779 "c" 10 bit breakpoint code (OP_*_CODE) 780 "d" 5 bit destination register specifier (OP_*_RD) 781 "h" 5 bit prefx hint (OP_*_PREFX) 782 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 783 "j" 16 bit signed immediate (OP_*_DELTA) 784 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 785 "o" 16 bit signed offset (OP_*_DELTA) 786 "p" 16 bit PC relative branch target address (OP_*_DELTA) 787 "q" 10 bit extra breakpoint code (OP_*_CODE2) 788 "r" 5 bit same register used as both source and target (OP_*_RS) 789 "s" 5 bit source register specifier (OP_*_RS) 790 "t" 5 bit target register (OP_*_RT) 791 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 792 "v" 5 bit same register used as both source and destination (OP_*_RS) 793 "w" 5 bit same register used as both target and destination (OP_*_RT) 794 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 795 (used by clo and clz) 796 "C" 25 bit coprocessor function code (OP_*_COPZ) 797 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 798 "J" 19 bit wait function code (OP_*_CODE19) 799 "x" accept and ignore register name 800 "z" must be zero register 801 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 802 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 803 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for 804 microMIPS compatibility). 805 Enforces: 0 <= pos < 32. 806 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 807 Requires that "+A" or "+E" occur first to set position. 808 Enforces: 0 < (pos+size) <= 32. 809 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 810 Requires that "+A" or "+E" occur first to set position. 811 Enforces: 0 < (pos+size) <= 32. 812 (Also used by "dext" w/ different limits, but limits for 813 that are checked by the M_DEXT macro.) 814 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 815 Enforces: 32 <= pos < 64. 816 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 817 Requires that "+A" or "+E" occur first to set position. 818 Enforces: 32 < (pos+size) <= 64. 819 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 820 Requires that "+A" or "+E" occur first to set position. 821 Enforces: 32 < (pos+size) <= 64. 822 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 823 Requires that "+A" or "+E" occur first to set position. 824 Enforces: 32 < (pos+size) <= 64. 825 826 Floating point instructions: 827 "D" 5 bit destination register (OP_*_FD) 828 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 829 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 830 "S" 5 bit fs source 1 register (OP_*_FS) 831 "T" 5 bit ft source 2 register (OP_*_FT) 832 "R" 5 bit fr source 3 register (OP_*_FR) 833 "V" 5 bit same register used as floating source and destination (OP_*_FS) 834 "W" 5 bit same register used as floating target and destination (OP_*_FT) 835 836 Coprocessor instructions: 837 "E" 5 bit target register (OP_*_RT) 838 "G" 5 bit destination register (OP_*_RD) 839 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 840 "P" 5 bit performance-monitor register (OP_*_PERFREG) 841 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 842 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 843 844 Macro instructions: 845 "A" General 32 bit expression 846 "I" 32 bit immediate (value placed in imm_expr). 847 "F" 64 bit floating point constant in .rdata 848 "L" 64 bit floating point constant in .lit8 849 "f" 32 bit floating point constant 850 "l" 32 bit floating point constant in .lit4 851 852 MDMX and VR5400 instruction operands (note that while these use the 853 FP register fields, the MDMX instructions accept both $fN and $vN names 854 for the registers): 855 "O" alignment offset (OP_*_ALN) 856 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 857 "X" destination register (OP_*_FD) 858 "Y" source register (OP_*_FS) 859 "Z" source register (OP_*_FT) 860 861 R5900 VU0 Macromode instructions: 862 "+5" 5 bit floating point register (FD) 863 "+6" 5 bit floating point register (FS) 864 "+7" 5 bit floating point register (FT) 865 "+8" 5 bit integer register (FD) 866 "+9" 5 bit integer register (FS) 867 "+0" 5 bit integer register (FT) 868 "+K" match an existing 4-bit channel mask starting at bit 21 869 "+L" 2-bit channel index starting at bit 21 870 "+M" 2-bit channel index starting at bit 23 871 "+N" match an existing 2-bit channel index starting at bit 0 872 "+f" 15 bit immediate for VCALLMS 873 "+g" 5 bit signed immediate for VIADDI 874 "+m" $ACC register (syntax only) 875 "+q" $Q register (syntax only) 876 "+r" $R register (syntax only) 877 "+y" $I register (syntax only) 878 "#+" "++" decorator in ($reg++) sequence 879 "#-" "--" decorator in (--$reg) sequence 880 881 DSP ASE usage: 882 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 883 "3" 3 bit unsigned immediate (OP_*_SA3) 884 "4" 4 bit unsigned immediate (OP_*_SA4) 885 "5" 8 bit unsigned immediate (OP_*_IMM8) 886 "6" 5 bit unsigned immediate (OP_*_RS) 887 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 888 "8" 6 bit unsigned immediate (OP_*_WRDSP) 889 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 890 "0" 6 bit signed immediate (OP_*_DSPSFT) 891 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 892 "'" 6 bit unsigned immediate (OP_*_RDDSP) 893 "@" 10 bit signed immediate (OP_*_IMM10) 894 895 MT ASE usage: 896 "!" 1 bit usermode flag (OP_*_MT_U) 897 "$" 1 bit load high flag (OP_*_MT_H) 898 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 899 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 900 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 901 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 902 903 MCU ASE usage: 904 "~" 12 bit offset (OP_*_OFFSET12) 905 "\" 3 bit position for aset and aclr (OP_*_3BITPOS) 906 907 VIRT ASE usage: 908 "+J" 10-bit hypcall code (OP_*CODE10) 909 910 UDI immediates: 911 "+1" UDI immediate bits 6-10 912 "+2" UDI immediate bits 6-15 913 "+3" UDI immediate bits 6-20 914 "+4" UDI immediate bits 6-25 915 916 Octeon: 917 "+x" Bit index field of bbit. Enforces: 0 <= index < 32. 918 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, 919 otherwise skips to next candidate. 920 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. 921 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 922 32 <= pos < 64, otherwise skips to next candidate. 923 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. 924 "+s" Length-minus-one field of cins32/exts32. Requires msb position 925 of the field to be <= 31. 926 "+S" Length-minus-one field of cins/exts. Requires msb position 927 of the field to be <= 63. 928 929 Loongson-3A: 930 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) 931 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) 932 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) 933 "+z" 5-bit rz register (OP_*_RZ) 934 "+Z" 5-bit fz register (OP_*_FZ) 935 936 Enhanced VA Scheme: 937 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) 938 939 MSA Extension: 940 "+d" 5-bit MSA register (FD) 941 "+e" 5-bit MSA register (FS) 942 "+h" 5-bit MSA register (FT) 943 "+k" 5-bit GPR at bit 6 944 "+l" 5-bit MSA control register at bit 6 945 "+n" 5-bit MSA control register at bit 11 946 "+o" 4-bit vector element index at bit 16 947 "+u" 3-bit vector element index at bit 16 948 "+v" 2-bit vector element index at bit 16 949 "+w" 1-bit vector element index at bit 16 950 "+T" (-512 .. 511) << 0 at bit 16 951 "+U" (-512 .. 511) << 1 at bit 16 952 "+V" (-512 .. 511) << 2 at bit 16 953 "+W" (-512 .. 511) << 3 at bit 16 954 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 955 "+!" 3 bit unsigned bit position at bit 16 956 "+@" 4 bit unsigned bit position at bit 16 957 "+#" 6 bit unsigned bit position at bit 16 958 "+$" 5 bit unsigned immediate at bit 16 959 "+%" 5 bit signed immediate at bit 16 960 "+^" 10 bit signed immediate at bit 11 961 "+&" 0 vector element index 962 "+*" 5-bit register vector element index at bit 16 963 "+|" 8-bit mask at bit 16 964 965 MIPS R6: 966 "+:" 11-bit mask at bit 0 967 "+'" 26 bit PC relative branch target address 968 "+"" 21 bit PC relative branch target address 969 "+;" 5 bit same register in both OP_*_RS and OP_*_RT 970 "+I" 2bit unsigned bit position at bit 6 971 "+O" 3bit unsigned bit position at bit 6 972 "+R" must be program counter 973 "-a" (-262144 .. 262143) << 2 at bit 0 974 "-b" (-131072 .. 131071) << 3 at bit 0 975 "-d" Same as destination register GP 976 "-s" 5 bit source register specifier (OP_*_RS) not $0 977 "-t" 5 bit source register specifier (OP_*_RT) not $0 978 "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS 979 "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS 980 "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS 981 "-x" 5 bit source register specifier (OP_*_RT) greater than or 982 equal to OP_*_RS 983 "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS 984 "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 985 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 986 987 Other: 988 "()" parens surrounding optional value 989 "," separates operands 990 "+" Start of extension sequence. 991 992 Characters used so far, for quick reference when adding more: 993 "1234567890" 994 "%[]<>(),+-:'@!#$*&\~" 995 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 996 "abcdefghijklopqrstuvwxz" 997 998 Extension character sequences used so far ("+" followed by the 999 following), for quick reference when adding more: 1000 "1234567890" 1001 "~!@#$%^&*|:'";" 1002 "ABCEFGHIJKLMNOPQRSTUVWXZ" 1003 "abcdefghijklmnopqrstuvwxyz" 1004 1005 Extension character sequences used so far ("-" followed by the 1006 following), for quick reference when adding more: 1007 "AB" 1008 "abdstuvwxy" 1009 1010 Extension character sequences used so far ("`" followed by the 1011 following), for quick reference when adding more: 1012 "ABEIOPTRSU" 1013 "abcdefgimopr" 1014 */ 1015 1016 /* These are the bits which may be set in the pinfo field of an 1017 instructions, if it is not equal to INSN_MACRO. */ 1018 1019 /* Writes to operand number N. */ 1020 #define INSN_WRITE_SHIFT 0 1021 #define INSN_WRITE_1 0x00000001 1022 #define INSN_WRITE_2 0x00000002 1023 #define INSN_WRITE_ALL 0x00000003 1024 /* Reads from operand number N. */ 1025 #define INSN_READ_SHIFT 2 1026 #define INSN_READ_1 0x00000004 1027 #define INSN_READ_2 0x00000008 1028 #define INSN_READ_3 0x00000010 1029 #define INSN_READ_4 0x00000020 1030 #define INSN_READ_ALL 0x0000003c 1031 /* Modifies general purpose register 31. */ 1032 #define INSN_WRITE_GPR_31 0x00000040 1033 /* Modifies coprocessor condition code. */ 1034 #define INSN_WRITE_COND_CODE 0x00000080 1035 /* Reads coprocessor condition code. */ 1036 #define INSN_READ_COND_CODE 0x00000100 1037 /* TLB operation. */ 1038 #define INSN_TLB 0x00000200 1039 /* Reads coprocessor register other than floating point register. */ 1040 #define INSN_COP 0x00000400 1041 /* Instruction loads value from memory. */ 1042 #define INSN_LOAD_MEMORY 0x00000800 1043 /* Instruction loads value from coprocessor, (may require delay). */ 1044 #define INSN_LOAD_COPROC 0x00001000 1045 /* Instruction has unconditional branch delay slot. */ 1046 #define INSN_UNCOND_BRANCH_DELAY 0x00002000 1047 /* Instruction has conditional branch delay slot. */ 1048 #define INSN_COND_BRANCH_DELAY 0x00004000 1049 /* Conditional branch likely: if branch not taken, insn nullified. */ 1050 #define INSN_COND_BRANCH_LIKELY 0x00008000 1051 /* Moves to coprocessor register, (may require delay). */ 1052 #define INSN_COPROC_MOVE 0x00010000 1053 /* Loads coprocessor register from memory, requiring delay. */ 1054 #define INSN_COPROC_MEMORY_DELAY 0x00020000 1055 /* Reads the HI register. */ 1056 #define INSN_READ_HI 0x00040000 1057 /* Reads the LO register. */ 1058 #define INSN_READ_LO 0x00080000 1059 /* Modifies the HI register. */ 1060 #define INSN_WRITE_HI 0x00100000 1061 /* Modifies the LO register. */ 1062 #define INSN_WRITE_LO 0x00200000 1063 /* Not to be placed in a branch delay slot, either architecturally 1064 or for ease of handling (such as with instructions that take a trap). */ 1065 #define INSN_NO_DELAY_SLOT 0x00400000 1066 /* Instruction stores value into memory. */ 1067 #define INSN_STORE_MEMORY 0x00800000 1068 /* Instruction uses single precision floating point. */ 1069 #define FP_S 0x01000000 1070 /* Instruction uses double precision floating point. */ 1071 #define FP_D 0x02000000 1072 /* Instruction is part of the tx39's integer multiply family. */ 1073 #define INSN_MULT 0x04000000 1074 /* Reads general purpose register 24. */ 1075 #define INSN_READ_GPR_24 0x08000000 1076 /* Writes to general purpose register 24. */ 1077 #define INSN_WRITE_GPR_24 0x10000000 1078 /* A user-defined instruction. */ 1079 #define INSN_UDI 0x20000000 1080 /* Instruction is actually a macro. It should be ignored by the 1081 disassembler, and requires special treatment by the assembler. */ 1082 #define INSN_MACRO 0xffffffff 1083 1084 /* These are the bits which may be set in the pinfo2 field of an 1085 instruction. */ 1086 1087 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 1088 #define INSN2_ALIAS 0x00000001 1089 /* Instruction reads MDMX accumulator. */ 1090 #define INSN2_READ_MDMX_ACC 0x00000002 1091 /* Instruction writes MDMX accumulator. */ 1092 #define INSN2_WRITE_MDMX_ACC 0x00000004 1093 /* Macro uses single-precision floating-point instructions. This should 1094 only be set for macros. For instructions, FP_S in pinfo carries the 1095 same information. */ 1096 #define INSN2_M_FP_S 0x00000008 1097 /* Macro uses double-precision floating-point instructions. This should 1098 only be set for macros. For instructions, FP_D in pinfo carries the 1099 same information. */ 1100 #define INSN2_M_FP_D 0x00000010 1101 /* Instruction has a branch delay slot that requires a 16-bit instruction. */ 1102 #define INSN2_BRANCH_DELAY_16BIT 0x00000020 1103 /* Instruction has a branch delay slot that requires a 32-bit instruction. */ 1104 #define INSN2_BRANCH_DELAY_32BIT 0x00000040 1105 /* Writes to the stack pointer ($29). */ 1106 #define INSN2_WRITE_SP 0x00000080 1107 /* Reads from the stack pointer ($29). */ 1108 #define INSN2_READ_SP 0x00000100 1109 /* Reads the RA ($31) register. */ 1110 #define INSN2_READ_GPR_31 0x00000200 1111 /* Reads the program counter ($pc). */ 1112 #define INSN2_READ_PC 0x00000400 1113 /* Is an unconditional branch insn. */ 1114 #define INSN2_UNCOND_BRANCH 0x00000800 1115 /* Is a conditional branch insn. */ 1116 #define INSN2_COND_BRANCH 0x00001000 1117 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */ 1118 #define INSN2_READ_GPR_16 0x00002000 1119 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ 1120 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 1121 /* Instruction has a forbidden slot. */ 1122 #define INSN2_FORBIDDEN_SLOT 0x00008000 1123 /* This indicates pre-R6 instructions mapped to R6 ones. */ 1124 #define INSN2_CONVERTED_TO_COMPACT 0x00010000 1125 1126 /* Masks used to mark instructions to indicate which MIPS ISA level 1127 they were introduced in. INSN_ISA_MASK masks an enumeration that 1128 specifies the base ISA level(s). The remainder of a 32-bit 1129 word constructed using these macros is a bitmask of the remaining 1130 INSN_* values below. */ 1131 1132 #define INSN_ISA_MASK 0x0000001ful 1133 1134 /* We cannot start at zero due to ISA_UNKNOWN below. */ 1135 #define INSN_ISA1 1 1136 #define INSN_ISA2 2 1137 #define INSN_ISA3 3 1138 #define INSN_ISA4 4 1139 #define INSN_ISA5 5 1140 #define INSN_ISA32 6 1141 #define INSN_ISA32R2 7 1142 #define INSN_ISA32R3 8 1143 #define INSN_ISA32R5 9 1144 #define INSN_ISA32R6 10 1145 #define INSN_ISA64 11 1146 #define INSN_ISA64R2 12 1147 #define INSN_ISA64R3 13 1148 #define INSN_ISA64R5 14 1149 #define INSN_ISA64R6 15 1150 /* Below this point the INSN_* values correspond to combinations of ISAs. 1151 They are only for use in the opcodes table to indicate membership of 1152 a combination of ISAs that cannot be expressed using the usual inclusion 1153 ordering on the above INSN_* values. */ 1154 #define INSN_ISA3_32 16 1155 #define INSN_ISA3_32R2 17 1156 #define INSN_ISA4_32 18 1157 #define INSN_ISA4_32R2 19 1158 #define INSN_ISA5_32R2 20 1159 1160 /* The R6 definitions shown below state that they support all previous ISAs. 1161 This is not actually true as some instructions are removed in R6. 1162 The problem is that the removed instructions in R6 come from different 1163 ISAs. One approach to solve this would be to describe in the membership 1164 field of the opcode table the different ISAs an instruction belongs to. 1165 This would require us to create a large amount of different ISA 1166 combinations which is hard to manage. A cleaner approach (which is 1167 implemented here) is to say that R6 is an extension of R5 and then to 1168 deal with the removed instructions by adding instruction exclusions 1169 for R6 in the opcode table. */ 1170 1171 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ 1172 1173 #define ISAF(X) (1 << (INSN_ISA##X - 1)) 1174 #define INSN_UPTO1 ISAF(1) 1175 #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) 1176 #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) 1177 #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) 1178 #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) 1179 #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) 1180 #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ 1181 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) 1182 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) 1183 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) 1184 #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) 1185 #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) 1186 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) 1187 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) 1188 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) 1189 #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) 1190 1191 /* The same information in table form: bit INSN_ISA<X> - 1 of index 1192 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ 1193 static const unsigned int mips_isa_table[] = { 1194 INSN_UPTO1, 1195 INSN_UPTO2, 1196 INSN_UPTO3, 1197 INSN_UPTO4, 1198 INSN_UPTO5, 1199 INSN_UPTO32, 1200 INSN_UPTO32R2, 1201 INSN_UPTO32R3, 1202 INSN_UPTO32R5, 1203 INSN_UPTO32R6, 1204 INSN_UPTO64, 1205 INSN_UPTO64R2, 1206 INSN_UPTO64R3, 1207 INSN_UPTO64R5, 1208 INSN_UPTO64R6 1209 }; 1210 #undef ISAF 1211 1212 /* Masks used for Chip specific instructions. */ 1213 #define INSN_CHIP_MASK 0xc3ff0f20 1214 1215 /* Cavium Networks Octeon instructions. */ 1216 #define INSN_OCTEON 0x00000800 1217 #define INSN_OCTEONP 0x00000200 1218 #define INSN_OCTEON2 0x00000100 1219 #define INSN_OCTEON3 0x00000040 1220 1221 /* MIPS R5900 instruction */ 1222 #define INSN_5900 0x00004000 1223 1224 /* MIPS R4650 instruction. */ 1225 #define INSN_4650 0x00010000 1226 /* LSI R4010 instruction. */ 1227 #define INSN_4010 0x00020000 1228 /* NEC VR4100 instruction. */ 1229 #define INSN_4100 0x00040000 1230 /* Toshiba R3900 instruction. */ 1231 #define INSN_3900 0x00080000 1232 /* MIPS R10000 instruction. */ 1233 #define INSN_10000 0x00100000 1234 /* Broadcom SB-1 instruction. */ 1235 #define INSN_SB1 0x00200000 1236 /* NEC VR4111/VR4181 instruction. */ 1237 #define INSN_4111 0x00400000 1238 /* NEC VR4120 instruction. */ 1239 #define INSN_4120 0x00800000 1240 /* NEC VR5400 instruction. */ 1241 #define INSN_5400 0x01000000 1242 /* NEC VR5500 instruction. */ 1243 #define INSN_5500 0x02000000 1244 1245 /* ST Microelectronics Loongson 2E. */ 1246 #define INSN_LOONGSON_2E 0x40000000 1247 /* ST Microelectronics Loongson 2F. */ 1248 #define INSN_LOONGSON_2F 0x80000000 1249 /* Loongson 3A. */ 1250 #define INSN_LOONGSON_3A 0x00000400 1251 /* RMI Xlr instruction */ 1252 #define INSN_XLR 0x00000020 1253 1254 /* DSP ASE */ 1255 #define ASE_DSP 0x00000001 1256 #define ASE_DSP64 0x00000002 1257 /* DSP R2 ASE */ 1258 #define ASE_DSPR2 0x00000004 1259 /* Enhanced VA Scheme */ 1260 #define ASE_EVA 0x00000008 1261 /* MCU (MicroController) ASE */ 1262 #define ASE_MCU 0x00000010 1263 /* MDMX ASE */ 1264 #define ASE_MDMX 0x00000020 1265 /* MIPS-3D ASE */ 1266 #define ASE_MIPS3D 0x00000040 1267 /* MT ASE */ 1268 #define ASE_MT 0x00000080 1269 /* SmartMIPS ASE */ 1270 #define ASE_SMARTMIPS 0x00000100 1271 /* Virtualization ASE */ 1272 #define ASE_VIRT 0x00000200 1273 #define ASE_VIRT64 0x00000400 1274 /* MSA Extension */ 1275 #define ASE_MSA 0x00000800 1276 #define ASE_MSA64 0x00001000 1277 /* eXtended Physical Address (XPA) Extension. */ 1278 #define ASE_XPA 0x00002000 1279 /* MXU Extension. */ 1280 #define ASE_MXU 0x00004000 1281 #define ASE_DSPR6 0x00008000 1282 1283 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 1284 1285 #define ISA_UNKNOWN 0 /* Gas internal use. */ 1286 #define ISA_MIPS1 INSN_ISA1 1287 #define ISA_MIPS2 INSN_ISA2 1288 #define ISA_MIPS3 INSN_ISA3 1289 #define ISA_MIPS4 INSN_ISA4 1290 #define ISA_MIPS5 INSN_ISA5 1291 1292 #define ISA_MIPS32 INSN_ISA32 1293 #define ISA_MIPS64 INSN_ISA64 1294 1295 #define ISA_MIPS32R2 INSN_ISA32R2 1296 #define ISA_MIPS32R3 INSN_ISA32R3 1297 #define ISA_MIPS32R5 INSN_ISA32R5 1298 #define ISA_MIPS64R2 INSN_ISA64R2 1299 #define ISA_MIPS64R3 INSN_ISA64R3 1300 #define ISA_MIPS64R5 INSN_ISA64R5 1301 1302 #define ISA_MIPS32R6 INSN_ISA32R6 1303 #define ISA_MIPS64R6 INSN_ISA64R6 1304 1305 /* CPU defines, use instead of hardcoding processor number. Keep this 1306 in sync with bfd/archures.c in order for machine selection to work. */ 1307 #define CPU_UNKNOWN 0 /* Gas internal use. */ 1308 #define CPU_R3000 3000 1309 #define CPU_R3900 3900 1310 #define CPU_R4000 4000 1311 #define CPU_R4010 4010 1312 #define CPU_VR4100 4100 1313 #define CPU_R4111 4111 1314 #define CPU_VR4120 4120 1315 #define CPU_R4300 4300 1316 #define CPU_R4400 4400 1317 #define CPU_R4600 4600 1318 #define CPU_R4650 4650 1319 #define CPU_R5000 5000 1320 #define CPU_VR5400 5400 1321 #define CPU_VR5500 5500 1322 #define CPU_R5900 5900 1323 #define CPU_R6000 6000 1324 #define CPU_RM7000 7000 1325 #define CPU_R8000 8000 1326 #define CPU_RM9000 9000 1327 #define CPU_R10000 10000 1328 #define CPU_R12000 12000 1329 #define CPU_R14000 14000 1330 #define CPU_R16000 16000 1331 #define CPU_MIPS16 16 1332 #define CPU_MIPS32 32 1333 #define CPU_MIPS32R2 33 1334 #define CPU_MIPS32R3 34 1335 #define CPU_MIPS32R5 36 1336 #define CPU_MIPS32R6 37 1337 #define CPU_MIPS5 5 1338 #define CPU_MIPS64 64 1339 #define CPU_MIPS64R2 65 1340 #define CPU_MIPS64R3 66 1341 #define CPU_MIPS64R5 68 1342 #define CPU_MIPS64R6 69 1343 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 1344 #define CPU_LOONGSON_2E 3001 1345 #define CPU_LOONGSON_2F 3002 1346 #define CPU_LOONGSON_3A 3003 1347 #define CPU_OCTEON 6501 1348 #define CPU_OCTEONP 6601 1349 #define CPU_OCTEON2 6502 1350 #define CPU_OCTEON3 6503 1351 #define CPU_XLR 887682 /* decimal 'XLR' */ 1352 1353 /* Return true if the given CPU is included in INSN_* mask MASK. */ 1354 1355 static inline bfd_boolean 1356 cpu_is_member (int cpu, unsigned int mask) 1357 { 1358 switch (cpu) 1359 { 1360 case CPU_R4650: 1361 case CPU_RM7000: 1362 case CPU_RM9000: 1363 return (mask & INSN_4650) != 0; 1364 1365 case CPU_R4010: 1366 return (mask & INSN_4010) != 0; 1367 1368 case CPU_VR4100: 1369 return (mask & INSN_4100) != 0; 1370 1371 case CPU_R3900: 1372 return (mask & INSN_3900) != 0; 1373 1374 case CPU_R10000: 1375 case CPU_R12000: 1376 case CPU_R14000: 1377 case CPU_R16000: 1378 return (mask & INSN_10000) != 0; 1379 1380 case CPU_SB1: 1381 return (mask & INSN_SB1) != 0; 1382 1383 case CPU_R4111: 1384 return (mask & INSN_4111) != 0; 1385 1386 case CPU_VR4120: 1387 return (mask & INSN_4120) != 0; 1388 1389 case CPU_VR5400: 1390 return (mask & INSN_5400) != 0; 1391 1392 case CPU_VR5500: 1393 return (mask & INSN_5500) != 0; 1394 1395 case CPU_R5900: 1396 return (mask & INSN_5900) != 0; 1397 1398 case CPU_LOONGSON_2E: 1399 return (mask & INSN_LOONGSON_2E) != 0; 1400 1401 case CPU_LOONGSON_2F: 1402 return (mask & INSN_LOONGSON_2F) != 0; 1403 1404 case CPU_LOONGSON_3A: 1405 return (mask & INSN_LOONGSON_3A) != 0; 1406 1407 case CPU_OCTEON: 1408 return (mask & INSN_OCTEON) != 0; 1409 1410 case CPU_OCTEONP: 1411 return (mask & INSN_OCTEONP) != 0; 1412 1413 case CPU_OCTEON2: 1414 return (mask & INSN_OCTEON2) != 0; 1415 1416 case CPU_OCTEON3: 1417 return (mask & INSN_OCTEON3) != 0; 1418 1419 case CPU_XLR: 1420 return (mask & INSN_XLR) != 0; 1421 1422 case CPU_MIPS32R6: 1423 return (mask & INSN_ISA_MASK) == INSN_ISA32R6; 1424 1425 case CPU_MIPS64R6: 1426 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) 1427 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); 1428 1429 default: 1430 return FALSE; 1431 } 1432 } 1433 1434 /* Test for membership in an ISA including chip specific ISAs. INSN 1435 is pointer to an element of the opcode table; ISA is the specified 1436 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 1437 test, or zero if no CPU specific ISA test is desired. Return true 1438 if instruction INSN is available to the given ISA and CPU. */ 1439 1440 static inline bfd_boolean 1441 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) 1442 { 1443 if (!cpu_is_member (cpu, insn->exclusions)) 1444 { 1445 /* Test for ISA level compatibility. */ 1446 if ((isa & INSN_ISA_MASK) != 0 1447 && (insn->membership & INSN_ISA_MASK) != 0 1448 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] 1449 >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) 1450 return TRUE; 1451 1452 /* Test for ASE compatibility. */ 1453 if ((ase & insn->ase) != 0) 1454 return TRUE; 1455 1456 /* Test for processor-specific extensions. */ 1457 if (cpu_is_member (cpu, insn->membership)) 1458 return TRUE; 1459 } 1460 return FALSE; 1461 } 1462 1463 /* This is a list of macro expanded instructions. 1464 1465 _I appended means immediate 1466 _A appended means target address of a jump 1467 _AB appended means address with (possibly zero) base register 1468 _D appended means 64 bit floating point constant 1469 _S appended means 32 bit floating point constant. */ 1470 1471 enum 1472 { 1473 M_ABS, 1474 M_ACLR_AB, 1475 M_ADD_I, 1476 M_ADDU_I, 1477 M_AND_I, 1478 M_ASET_AB, 1479 M_BALIGN, 1480 M_BC1FL, 1481 M_BC1TL, 1482 M_BC2FL, 1483 M_BC2TL, 1484 M_BEQ, 1485 M_BEQ_I, 1486 M_BEQL, 1487 M_BEQL_I, 1488 M_BGE, 1489 M_BGEL, 1490 M_BGE_I, 1491 M_BGEL_I, 1492 M_BGEU, 1493 M_BGEUL, 1494 M_BGEU_I, 1495 M_BGEUL_I, 1496 M_BGEZ, 1497 M_BGEZL, 1498 M_BGEZALL, 1499 M_BGT, 1500 M_BGTL, 1501 M_BGT_I, 1502 M_BGTL_I, 1503 M_BGTU, 1504 M_BGTUL, 1505 M_BGTU_I, 1506 M_BGTUL_I, 1507 M_BGTZ, 1508 M_BGTZL, 1509 M_BLE, 1510 M_BLEL, 1511 M_BLE_I, 1512 M_BLEL_I, 1513 M_BLEU, 1514 M_BLEUL, 1515 M_BLEU_I, 1516 M_BLEUL_I, 1517 M_BLEZ, 1518 M_BLEZL, 1519 M_BLT, 1520 M_BLTL, 1521 M_BLT_I, 1522 M_BLTL_I, 1523 M_BLTU, 1524 M_BLTUL, 1525 M_BLTU_I, 1526 M_BLTUL_I, 1527 M_BLTZ, 1528 M_BLTZL, 1529 M_BLTZALL, 1530 M_BNE, 1531 M_BNEL, 1532 M_BNE_I, 1533 M_BNEL_I, 1534 M_CACHE_AB, 1535 M_CACHEE_AB, 1536 M_DABS, 1537 M_DADD_I, 1538 M_DADDU_I, 1539 M_DDIV_3, 1540 M_DDIV_3I, 1541 M_DDIVU_3, 1542 M_DDIVU_3I, 1543 M_DIV_3, 1544 M_DIV_3I, 1545 M_DIVU_3, 1546 M_DIVU_3I, 1547 M_DLA_AB, 1548 M_DLCA_AB, 1549 M_DLI, 1550 M_DMUL, 1551 M_DMUL_I, 1552 M_DMULO, 1553 M_DMULO_I, 1554 M_DMULOU, 1555 M_DMULOU_I, 1556 M_DREM_3, 1557 M_DREM_3I, 1558 M_DREMU_3, 1559 M_DREMU_3I, 1560 M_DSUB_I, 1561 M_DSUBU_I, 1562 M_DSUBU_I_2, 1563 M_J_A, 1564 M_JAL_1, 1565 M_JAL_2, 1566 M_JAL_A, 1567 M_JALS_1, 1568 M_JALS_2, 1569 M_JALS_A, 1570 M_JRADDIUSP, 1571 M_JRC, 1572 M_L_DAB, 1573 M_LA_AB, 1574 M_LB_AB, 1575 M_LBE_AB, 1576 M_LBU_AB, 1577 M_LBUE_AB, 1578 M_LCA_AB, 1579 M_LD_AB, 1580 M_LDC1_AB, 1581 M_LDC2_AB, 1582 M_LQC2_AB, 1583 M_LDC3_AB, 1584 M_LDL_AB, 1585 M_LDM_AB, 1586 M_LDP_AB, 1587 M_LDR_AB, 1588 M_LH_AB, 1589 M_LHE_AB, 1590 M_LHU_AB, 1591 M_LHUE_AB, 1592 M_LI, 1593 M_LI_D, 1594 M_LI_DD, 1595 M_LI_S, 1596 M_LI_SS, 1597 M_LL_AB, 1598 M_LLD_AB, 1599 M_LLE_AB, 1600 M_LQ_AB, 1601 M_LW_AB, 1602 M_LWE_AB, 1603 M_LWC0_AB, 1604 M_LWC1_AB, 1605 M_LWC2_AB, 1606 M_LWC3_AB, 1607 M_LWL_AB, 1608 M_LWLE_AB, 1609 M_LWM_AB, 1610 M_LWP_AB, 1611 M_LWR_AB, 1612 M_LWRE_AB, 1613 M_LWU_AB, 1614 M_MSGSND, 1615 M_MSGLD, 1616 M_MSGLD_T, 1617 M_MSGWAIT, 1618 M_MSGWAIT_T, 1619 M_MOVE, 1620 M_MOVEP, 1621 M_MUL, 1622 M_MUL_I, 1623 M_MULO, 1624 M_MULO_I, 1625 M_MULOU, 1626 M_MULOU_I, 1627 M_NOR_I, 1628 M_OR_I, 1629 M_PREF_AB, 1630 M_PREFE_AB, 1631 M_REM_3, 1632 M_REM_3I, 1633 M_REMU_3, 1634 M_REMU_3I, 1635 M_DROL, 1636 M_ROL, 1637 M_DROL_I, 1638 M_ROL_I, 1639 M_DROR, 1640 M_ROR, 1641 M_DROR_I, 1642 M_ROR_I, 1643 M_S_DA, 1644 M_S_DAB, 1645 M_S_S, 1646 M_SAA_AB, 1647 M_SAAD_AB, 1648 M_SC_AB, 1649 M_SCD_AB, 1650 M_SCE_AB, 1651 M_SD_AB, 1652 M_SDC1_AB, 1653 M_SDC2_AB, 1654 M_SQC2_AB, 1655 M_SDC3_AB, 1656 M_SDL_AB, 1657 M_SDM_AB, 1658 M_SDP_AB, 1659 M_SDR_AB, 1660 M_SEQ, 1661 M_SEQ_I, 1662 M_SGE, 1663 M_SGE_I, 1664 M_SGEU, 1665 M_SGEU_I, 1666 M_SGT, 1667 M_SGT_I, 1668 M_SGTU, 1669 M_SGTU_I, 1670 M_SLE, 1671 M_SLE_I, 1672 M_SLEU, 1673 M_SLEU_I, 1674 M_SLT_I, 1675 M_SLTU_I, 1676 M_SNE, 1677 M_SNE_I, 1678 M_SB_AB, 1679 M_SBE_AB, 1680 M_SH_AB, 1681 M_SHE_AB, 1682 M_SQ_AB, 1683 M_SW_AB, 1684 M_SWE_AB, 1685 M_SWC0_AB, 1686 M_SWC1_AB, 1687 M_SWC2_AB, 1688 M_SWC3_AB, 1689 M_SWL_AB, 1690 M_SWLE_AB, 1691 M_SWM_AB, 1692 M_SWP_AB, 1693 M_SWR_AB, 1694 M_SWRE_AB, 1695 M_SUB_I, 1696 M_SUBU_I, 1697 M_SUBU_I_2, 1698 M_TEQ_I, 1699 M_TGE_I, 1700 M_TGEU_I, 1701 M_TLT_I, 1702 M_TLTU_I, 1703 M_TNE_I, 1704 M_TRUNCWD, 1705 M_TRUNCWS, 1706 M_ULD_AB, 1707 M_ULH_AB, 1708 M_ULHU_AB, 1709 M_ULW_AB, 1710 M_USH_AB, 1711 M_USW_AB, 1712 M_USD_AB, 1713 M_XOR_I, 1714 M_COP0, 1715 M_COP1, 1716 M_COP2, 1717 M_COP3, 1718 M_NUM_MACROS 1719 }; 1720 1721 1722 /* The order of overloaded instructions matters. Label arguments and 1723 register arguments look the same. Instructions that can have either 1724 for arguments must apear in the correct order in this table for the 1725 assembler to pick the right one. In other words, entries with 1726 immediate operands must apear after the same instruction with 1727 registers. 1728 1729 Many instructions are short hand for other instructions (i.e., The 1730 jal <register> instruction is short for jalr <register>). */ 1731 1732 extern const struct mips_operand mips_vu0_channel_mask; 1733 extern const struct mips_operand *decode_mips_operand (const char *); 1734 extern const struct mips_opcode mips_builtin_opcodes[]; 1735 extern const int bfd_mips_num_builtin_opcodes; 1736 extern struct mips_opcode *mips_opcodes; 1737 extern int bfd_mips_num_opcodes; 1738 #define NUMOPCODES bfd_mips_num_opcodes 1739 1740 1741 /* The rest of this file adds definitions for the mips16 TinyRISC 1743 processor. */ 1744 1745 /* These are the bitmasks and shift counts used for the different 1746 fields in the instruction formats. Other than OP, no masks are 1747 provided for the fixed portions of an instruction, since they are 1748 not needed. 1749 1750 The I format uses IMM11. 1751 1752 The RI format uses RX and IMM8. 1753 1754 The RR format uses RX, and RY. 1755 1756 The RRI format uses RX, RY, and IMM5. 1757 1758 The RRR format uses RX, RY, and RZ. 1759 1760 The RRI_A format uses RX, RY, and IMM4. 1761 1762 The SHIFT format uses RX, RY, and SHAMT. 1763 1764 The I8 format uses IMM8. 1765 1766 The I8_MOVR32 format uses RY and REGR32. 1767 1768 The IR_MOV32R format uses REG32R and MOV32Z. 1769 1770 The I64 format uses IMM8. 1771 1772 The RI64 format uses RY and IMM5. 1773 */ 1774 1775 #define MIPS16OP_MASK_OP 0x1f 1776 #define MIPS16OP_SH_OP 11 1777 #define MIPS16OP_MASK_IMM11 0x7ff 1778 #define MIPS16OP_SH_IMM11 0 1779 #define MIPS16OP_MASK_RX 0x7 1780 #define MIPS16OP_SH_RX 8 1781 #define MIPS16OP_MASK_IMM8 0xff 1782 #define MIPS16OP_SH_IMM8 0 1783 #define MIPS16OP_MASK_RY 0x7 1784 #define MIPS16OP_SH_RY 5 1785 #define MIPS16OP_MASK_IMM5 0x1f 1786 #define MIPS16OP_SH_IMM5 0 1787 #define MIPS16OP_MASK_RZ 0x7 1788 #define MIPS16OP_SH_RZ 2 1789 #define MIPS16OP_MASK_IMM4 0xf 1790 #define MIPS16OP_SH_IMM4 0 1791 #define MIPS16OP_MASK_REGR32 0x1f 1792 #define MIPS16OP_SH_REGR32 0 1793 #define MIPS16OP_MASK_REG32R 0x1f 1794 #define MIPS16OP_SH_REG32R 3 1795 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 1796 #define MIPS16OP_MASK_MOVE32Z 0x7 1797 #define MIPS16OP_SH_MOVE32Z 0 1798 #define MIPS16OP_MASK_IMM6 0x3f 1799 #define MIPS16OP_SH_IMM6 5 1800 1801 /* These are the characters which may appears in the args field of a MIPS16 1802 instruction. They appear in the order in which the fields appear when the 1803 instruction is used. Commas and parentheses in the args string are ignored 1804 when assembling, and written into the output when disassembling. 1805 1806 "y" 3 bit register (MIPS16OP_*_RY) 1807 "x" 3 bit register (MIPS16OP_*_RX) 1808 "z" 3 bit register (MIPS16OP_*_RZ) 1809 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1810 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1811 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1812 "0" zero register ($0) 1813 "S" stack pointer ($sp or $29) 1814 "P" program counter 1815 "R" return address register ($ra or $31) 1816 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1817 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1818 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1819 "a" 26 bit jump address 1820 "i" likewise, but flips bit 0 1821 "e" 11 bit extension value 1822 "l" register list for entry instruction 1823 "L" register list for exit instruction 1824 1825 "I" an immediate value used for macros 1826 1827 The remaining codes may be extended. Except as otherwise noted, 1828 the full extended operand is a 16 bit signed value. 1829 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1830 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 1831 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1832 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1833 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1834 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1835 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1836 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1837 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1838 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1839 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1840 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1841 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1842 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1843 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1844 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1845 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1846 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1847 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1848 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1849 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1850 "m" 7 bit register list for save instruction (18 bit extended) 1851 "M" 7 bit register list for restore instruction (18 bit extended) 1852 */ 1853 1854 /* Save/restore encoding for the args field when all 4 registers are 1855 either saved as arguments or saved/restored as statics. */ 1856 #define MIPS16_ALL_ARGS 0xe 1857 #define MIPS16_ALL_STATICS 0xb 1858 1859 /* The following flags have the same value for the mips16 opcode 1860 table: 1861 1862 INSN_ISA3 1863 1864 INSN_UNCOND_BRANCH_DELAY 1865 INSN_COND_BRANCH_DELAY 1866 INSN_COND_BRANCH_LIKELY (never used) 1867 INSN_READ_HI 1868 INSN_READ_LO 1869 INSN_WRITE_HI 1870 INSN_WRITE_LO 1871 INSN_TRAP 1872 FP_D (never used) 1873 */ 1874 1875 extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); 1876 extern const struct mips_opcode mips16_opcodes[]; 1877 extern const int bfd_mips16_num_opcodes; 1878 1879 /* These are the bit masks and shift counts used for the different fields 1880 in the microMIPS instruction formats. No masks are provided for the 1881 fixed portions of an instruction, since they are not needed. */ 1882 1883 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff 1884 #define MICROMIPSOP_SH_IMMEDIATE 0 1885 #define MICROMIPSOP_MASK_DELTA 0xffff 1886 #define MICROMIPSOP_SH_DELTA 0 1887 #define MICROMIPSOP_MASK_CODE10 0x3ff 1888 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ 1889 #define MICROMIPSOP_MASK_TRAP 0xf 1890 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ 1891 #define MICROMIPSOP_MASK_SHAMT 0x1f 1892 #define MICROMIPSOP_SH_SHAMT 11 1893 #define MICROMIPSOP_MASK_TARGET 0x3ffffff 1894 #define MICROMIPSOP_SH_TARGET 0 1895 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ 1896 #define MICROMIPSOP_SH_EXTLSB 6 1897 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 1898 #define MICROMIPSOP_SH_EXTMSBD 11 1899 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ 1900 #define MICROMIPSOP_SH_INSMSB 11 1901 #define MICROMIPSOP_MASK_CODE 0x3ff 1902 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ 1903 #define MICROMIPSOP_MASK_CODE2 0x3ff 1904 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ 1905 #define MICROMIPSOP_MASK_CACHE 0x1f 1906 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ 1907 #define MICROMIPSOP_MASK_SEL 0x7 1908 #define MICROMIPSOP_SH_SEL 11 1909 #define MICROMIPSOP_MASK_OFFSET12 0xfff 1910 #define MICROMIPSOP_SH_OFFSET12 0 1911 #define MICROMIPSOP_MASK_3BITPOS 0x7 1912 #define MICROMIPSOP_SH_3BITPOS 21 1913 #define MICROMIPSOP_MASK_STYPE 0x1f 1914 #define MICROMIPSOP_SH_STYPE 16 1915 #define MICROMIPSOP_MASK_OFFSET10 0x3ff 1916 #define MICROMIPSOP_SH_OFFSET10 6 1917 #define MICROMIPSOP_MASK_RS 0x1f 1918 #define MICROMIPSOP_SH_RS 16 1919 #define MICROMIPSOP_MASK_RT 0x1f 1920 #define MICROMIPSOP_SH_RT 21 1921 #define MICROMIPSOP_MASK_RD 0x1f 1922 #define MICROMIPSOP_SH_RD 11 1923 #define MICROMIPSOP_MASK_FS 0x1f 1924 #define MICROMIPSOP_SH_FS 16 1925 #define MICROMIPSOP_MASK_FT 0x1f 1926 #define MICROMIPSOP_SH_FT 21 1927 #define MICROMIPSOP_MASK_FD 0x1f 1928 #define MICROMIPSOP_SH_FD 11 1929 #define MICROMIPSOP_MASK_FR 0x1f 1930 #define MICROMIPSOP_SH_FR 6 1931 #define MICROMIPSOP_MASK_RS3 0x1f 1932 #define MICROMIPSOP_SH_RS3 6 1933 #define MICROMIPSOP_MASK_PREFX 0x1f 1934 #define MICROMIPSOP_SH_PREFX 11 1935 #define MICROMIPSOP_MASK_BCC 0x7 1936 #define MICROMIPSOP_SH_BCC 18 1937 #define MICROMIPSOP_MASK_CCC 0x7 1938 #define MICROMIPSOP_SH_CCC 13 1939 #define MICROMIPSOP_MASK_COPZ 0x7fffff 1940 #define MICROMIPSOP_SH_COPZ 3 1941 1942 #define MICROMIPSOP_MASK_MB 0x7 1943 #define MICROMIPSOP_SH_MB 23 1944 #define MICROMIPSOP_MASK_MC 0x7 1945 #define MICROMIPSOP_SH_MC 4 1946 #define MICROMIPSOP_MASK_MD 0x7 1947 #define MICROMIPSOP_SH_MD 7 1948 #define MICROMIPSOP_MASK_ME 0x7 1949 #define MICROMIPSOP_SH_ME 1 1950 #define MICROMIPSOP_MASK_MF 0x7 1951 #define MICROMIPSOP_SH_MF 3 1952 #define MICROMIPSOP_MASK_MG 0x7 1953 #define MICROMIPSOP_SH_MG 0 1954 #define MICROMIPSOP_MASK_MH 0x7 1955 #define MICROMIPSOP_SH_MH 7 1956 #define MICROMIPSOP_MASK_MJ 0x1f 1957 #define MICROMIPSOP_SH_MJ 0 1958 #define MICROMIPSOP_MASK_ML 0x7 1959 #define MICROMIPSOP_SH_ML 4 1960 #define MICROMIPSOP_MASK_MM 0x7 1961 #define MICROMIPSOP_SH_MM 1 1962 #define MICROMIPSOP_MASK_MN 0x7 1963 #define MICROMIPSOP_SH_MN 4 1964 #define MICROMIPSOP_MASK_MP 0x1f 1965 #define MICROMIPSOP_SH_MP 5 1966 #define MICROMIPSOP_MASK_MQ 0x7 1967 #define MICROMIPSOP_SH_MQ 7 1968 1969 #define MICROMIPSOP_MASK_IMMA 0x7f 1970 #define MICROMIPSOP_SH_IMMA 0 1971 #define MICROMIPSOP_MASK_IMMB 0x7 1972 #define MICROMIPSOP_SH_IMMB 1 1973 #define MICROMIPSOP_MASK_IMMC 0xf 1974 #define MICROMIPSOP_SH_IMMC 0 1975 #define MICROMIPSOP_MASK_IMMD 0x3ff 1976 #define MICROMIPSOP_SH_IMMD 0 1977 #define MICROMIPSOP_MASK_IMME 0x7f 1978 #define MICROMIPSOP_SH_IMME 0 1979 #define MICROMIPSOP_MASK_IMMF 0xf 1980 #define MICROMIPSOP_SH_IMMF 0 1981 #define MICROMIPSOP_MASK_IMMG 0xf 1982 #define MICROMIPSOP_SH_IMMG 0 1983 #define MICROMIPSOP_MASK_IMMH 0xf 1984 #define MICROMIPSOP_SH_IMMH 0 1985 #define MICROMIPSOP_MASK_IMMI 0x7f 1986 #define MICROMIPSOP_SH_IMMI 0 1987 #define MICROMIPSOP_MASK_IMMJ 0xf 1988 #define MICROMIPSOP_SH_IMMJ 0 1989 #define MICROMIPSOP_MASK_IMML 0xf 1990 #define MICROMIPSOP_SH_IMML 0 1991 #define MICROMIPSOP_MASK_IMMM 0x7 1992 #define MICROMIPSOP_SH_IMMM 1 1993 #define MICROMIPSOP_MASK_IMMN 0x3 1994 #define MICROMIPSOP_SH_IMMN 4 1995 #define MICROMIPSOP_MASK_IMMO 0xf 1996 #define MICROMIPSOP_SH_IMMO 0 1997 #define MICROMIPSOP_MASK_IMMP 0x1f 1998 #define MICROMIPSOP_SH_IMMP 0 1999 #define MICROMIPSOP_MASK_IMMQ 0x7fffff 2000 #define MICROMIPSOP_SH_IMMQ 0 2001 #define MICROMIPSOP_MASK_IMMU 0x1f 2002 #define MICROMIPSOP_SH_IMMU 0 2003 #define MICROMIPSOP_MASK_IMMW 0x3f 2004 #define MICROMIPSOP_SH_IMMW 1 2005 #define MICROMIPSOP_MASK_IMMX 0xf 2006 #define MICROMIPSOP_SH_IMMX 1 2007 #define MICROMIPSOP_MASK_IMMY 0x1ff 2008 #define MICROMIPSOP_SH_IMMY 1 2009 2010 /* MIPS DSP ASE */ 2011 #define MICROMIPSOP_MASK_DSPACC 0x3 2012 #define MICROMIPSOP_SH_DSPACC 14 2013 #define MICROMIPSOP_MASK_DSPSFT 0x3f 2014 #define MICROMIPSOP_SH_DSPSFT 16 2015 #define MICROMIPSOP_MASK_SA3 0x7 2016 #define MICROMIPSOP_SH_SA3 13 2017 #define MICROMIPSOP_MASK_SA4 0xf 2018 #define MICROMIPSOP_SH_SA4 12 2019 #define MICROMIPSOP_MASK_IMM8 0xff 2020 #define MICROMIPSOP_SH_IMM8 13 2021 #define MICROMIPSOP_MASK_IMM10 0x3ff 2022 #define MICROMIPSOP_SH_IMM10 16 2023 #define MICROMIPSOP_MASK_WRDSP 0x3f 2024 #define MICROMIPSOP_SH_WRDSP 14 2025 #define MICROMIPSOP_MASK_BP 0x3 2026 #define MICROMIPSOP_SH_BP 14 2027 2028 /* Placeholders for fields that only exist in the traditional 32-bit 2029 instruction encoding; see the comment above for details. */ 2030 #define MICROMIPSOP_MASK_CODE20 0 2031 #define MICROMIPSOP_SH_CODE20 0 2032 #define MICROMIPSOP_MASK_PERFREG 0 2033 #define MICROMIPSOP_SH_PERFREG 0 2034 #define MICROMIPSOP_MASK_CODE19 0 2035 #define MICROMIPSOP_SH_CODE19 0 2036 #define MICROMIPSOP_MASK_ALN 0 2037 #define MICROMIPSOP_SH_ALN 0 2038 #define MICROMIPSOP_MASK_VECBYTE 0 2039 #define MICROMIPSOP_SH_VECBYTE 0 2040 #define MICROMIPSOP_MASK_VECALIGN 0 2041 #define MICROMIPSOP_SH_VECALIGN 0 2042 #define MICROMIPSOP_MASK_DSPACC_S 0 2043 #define MICROMIPSOP_SH_DSPACC_S 0 2044 #define MICROMIPSOP_MASK_DSPSFT_7 0 2045 #define MICROMIPSOP_SH_DSPSFT_7 0 2046 #define MICROMIPSOP_MASK_RDDSP 0 2047 #define MICROMIPSOP_SH_RDDSP 0 2048 #define MICROMIPSOP_MASK_MT_U 0 2049 #define MICROMIPSOP_SH_MT_U 0 2050 #define MICROMIPSOP_MASK_MT_H 0 2051 #define MICROMIPSOP_SH_MT_H 0 2052 #define MICROMIPSOP_MASK_MTACC_T 0 2053 #define MICROMIPSOP_SH_MTACC_T 0 2054 #define MICROMIPSOP_MASK_MTACC_D 0 2055 #define MICROMIPSOP_SH_MTACC_D 0 2056 #define MICROMIPSOP_MASK_BBITIND 0 2057 #define MICROMIPSOP_SH_BBITIND 0 2058 #define MICROMIPSOP_MASK_CINSPOS 0 2059 #define MICROMIPSOP_SH_CINSPOS 0 2060 #define MICROMIPSOP_MASK_CINSLM1 0 2061 #define MICROMIPSOP_SH_CINSLM1 0 2062 #define MICROMIPSOP_MASK_SEQI 0 2063 #define MICROMIPSOP_SH_SEQI 0 2064 #define MICROMIPSOP_SH_OFFSET_A 0 2065 #define MICROMIPSOP_MASK_OFFSET_A 0 2066 #define MICROMIPSOP_SH_OFFSET_B 0 2067 #define MICROMIPSOP_MASK_OFFSET_B 0 2068 #define MICROMIPSOP_SH_OFFSET_C 0 2069 #define MICROMIPSOP_MASK_OFFSET_C 0 2070 #define MICROMIPSOP_SH_RZ 0 2071 #define MICROMIPSOP_MASK_RZ 0 2072 #define MICROMIPSOP_SH_FZ 0 2073 #define MICROMIPSOP_MASK_FZ 0 2074 2075 /* microMIPS Enhanced VA Scheme */ 2076 #define MICROMIPSOP_SH_EVAOFFSET 0 2077 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff 2078 2079 /* These are the characters which may appears in the args field of a microMIPS 2080 instruction. They appear in the order in which the fields appear 2081 when the instruction is used. Commas and parentheses in the args 2082 string are ignored when assembling, and written into the output 2083 when disassembling. 2084 2085 The followings are for 16-bit microMIPS instructions. 2086 2087 "ma" must be $28 2088 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 2089 The same register used as both source and target. 2090 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 2091 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 2092 The same register used as both source and target. 2093 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 2094 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 2095 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 2096 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 2097 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 2098 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 2099 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 2100 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 2101 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 2102 "mr" must be program counter 2103 "ms" must be $29 2104 "mt" must be the same as the previous register 2105 "mx" must be the same as the destination register 2106 "my" must be $31 2107 "mz" must be $0 2108 2109 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) 2110 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) 2111 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, 2112 32768, 65535) (MICROMIPSOP_*_IMMC) 2113 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) 2114 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) 2115 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) 2116 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) 2117 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) 2118 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) 2119 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) 2120 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2121 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) 2122 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) 2123 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2124 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) 2125 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) 2126 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) 2127 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) 2128 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) 2129 "mZ" must be zero 2130 2131 In most cases 32-bit microMIPS instructions use the same characters 2132 as MIPS (with ADDIUPC being a notable exception, but there are some 2133 others too). 2134 2135 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) 2136 "1" 5-bit sync type (MICROMIPSOP_*_STYPE) 2137 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) 2138 ">" shift amount between 32 and 63, stored after subtracting 32 2139 (MICROMIPSOP_*_SHAMT) 2140 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) 2141 "|" 4-bit trap code (MICROMIPSOP_*_TRAP) 2142 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) 2143 "a" 26-bit target address (MICROMIPSOP_*_TARGET) 2144 "+i" likewise, but flips bit 0 2145 "b" 5-bit base register (MICROMIPSOP_*_RS) 2146 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) 2147 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) 2148 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) 2149 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) 2150 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) 2151 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) 2152 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) 2153 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) 2154 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) 2155 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) 2156 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) 2157 "s" 5-bit source register specifier (MICROMIPSOP_*_RS) 2158 "t" 5-bit target register (MICROMIPSOP_*_RT) 2159 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) 2160 "v" 5-bit same register used as both source and destination 2161 (MICROMIPSOP_*_RS) 2162 "w" 5-bit same register used as both target and destination 2163 (MICROMIPSOP_*_RT) 2164 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) 2165 "z" must be zero register 2166 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) 2167 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) 2168 2169 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes 2170 LSB (MICROMIPSOP_*_EXTLSB). 2171 Enforces: 0 <= pos < 32. 2172 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). 2173 Requires that "+A" or "+E" occur first to set position. 2174 Enforces: 0 < (pos+size) <= 32. 2175 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2176 Requires that "+A" or "+E" occur first to set position. 2177 Enforces: 0 < (pos+size) <= 32. 2178 (Also used by DEXT w/ different limits, but limits for 2179 that are checked by the M_DEXT macro.) 2180 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). 2181 Enforces: 32 <= pos < 64. 2182 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). 2183 Requires that "+A" or "+E" occur first to set position. 2184 Enforces: 32 < (pos+size) <= 64. 2185 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). 2186 Requires that "+A" or "+E" occur first to set position. 2187 Enforces: 32 < (pos+size) <= 64. 2188 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2189 Requires that "+A" or "+E" occur first to set position. 2190 Enforces: 32 < (pos+size) <= 64. 2191 "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code 2192 (MICROMIPSOP_*_CODE10) 2193 2194 PC-relative addition (ADDIUPC) instruction: 2195 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) 2196 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 2197 2198 Floating point instructions: 2199 "D" 5-bit destination register (MICROMIPSOP_*_FD) 2200 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) 2201 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) 2202 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) 2203 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) 2204 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) 2205 "V" 5-bit same register used as floating source and destination or target 2206 (MICROMIPSOP_*_FS) 2207 2208 Coprocessor instructions: 2209 "E" 5-bit target register (MICROMIPSOP_*_RT) 2210 "G" 5-bit source register (MICROMIPSOP_*_RS) 2211 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) 2212 2213 Macro instructions: 2214 "A" general 32 bit expression 2215 "I" 32-bit immediate (value placed in imm_expr). 2216 "F" 64-bit floating point constant in .rdata 2217 "L" 64-bit floating point constant in .lit8 2218 "f" 32-bit floating point constant 2219 "l" 32-bit floating point constant in .lit4 2220 2221 DSP ASE usage: 2222 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) 2223 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) 2224 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) 2225 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) 2226 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) 2227 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) 2228 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) 2229 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) 2230 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) 2231 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) 2232 2233 microMIPS Enhanced VA Scheme: 2234 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) 2235 2236 MSA Extension: 2237 "+d" 5-bit MSA register (FD) 2238 "+e" 5-bit MSA register (FS) 2239 "+h" 5-bit MSA register (FT) 2240 "+k" 5-bit GPR at bit 6 2241 "+l" 5-bit MSA control register at bit 6 2242 "+n" 5-bit MSA control register at bit 11 2243 "+o" 4-bit vector element index at bit 16 2244 "+u" 3-bit vector element index at bit 16 2245 "+v" 2-bit vector element index at bit 16 2246 "+w" 1-bit vector element index at bit 16 2247 "+x" 5-bit shift amount at bit 16 2248 "+T" (-512 .. 511) << 0 at bit 16 2249 "+U" (-512 .. 511) << 1 at bit 16 2250 "+V" (-512 .. 511) << 2 at bit 16 2251 "+W" (-512 .. 511) << 3 at bit 16 2252 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 2253 "+!" 3 bit unsigned bit position at bit 16 2254 "+@" 4 bit unsigned bit position at bit 16 2255 "+#" 6 bit unsigned bit position at bit 16 2256 "+$" 5 bit unsigned immediate at bit 16 2257 "+%" 5 bit signed immediate at bit 16 2258 "+^" 10 bit signed immediate at bit 11 2259 "+&" 0 vector element index 2260 "+*" 5-bit register vector element index at bit 16 2261 "+|" 8-bit mask at bit 16 2262 2263 Other: 2264 "()" parens surrounding optional value 2265 "," separates operands 2266 "+" start of extension sequence 2267 "m" start of microMIPS extension sequence 2268 2269 Characters used so far, for quick reference when adding more: 2270 "12345678 0" 2271 "<>(),+-.@\^|~" 2272 "ABCDEFGHI KLMN RST V " 2273 "abcd f hijklmnopqrstuvw yz" 2274 2275 Extension character sequences used so far ("+" followed by the 2276 following), for quick reference when adding more: 2277 "" 2278 "~!@#$%^&*|" 2279 "ABCEFGHJTUVW" 2280 "dehijklnouvwx" 2281 2282 Extension character sequences used so far ("m" followed by the 2283 following), for quick reference when adding more: 2284 "" 2285 "" 2286 " BCDEFGHIJ LMNOPQ U WXYZ" 2287 " bcdefghij lmn pq st xyz" 2288 2289 Extension character sequences used so far ("-" followed by the 2290 following), for quick reference when adding more: 2291 "" 2292 "" 2293 <none so far> 2294 */ 2295 2296 extern const struct mips_operand *decode_micromips_operand (const char *); 2297 extern const struct mips_opcode micromips_opcodes[]; 2298 extern const int bfd_micromips_num_opcodes; 2299 2300 /* A NOP insn impemented as "or at,at,zero". 2301 Used to implement -mfix-loongson2f. */ 2302 #define LOONGSON2F_NOP_INSN 0x00200825 2303 2304 #endif /* _MIPS_H_ */ 2305
