| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
365 Inst.addOperand(MCOperand::createImm(Op1));
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreSelectionDAGInfo.h | 29 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC))
189 if (match(Op1, m_AllOnes())) {
243 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
269 if (isa<Constant>(Op1)) {
284 Value *Mul = Builder->CreateMul(C1, Op1);
288 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul);
294 if (Value *Op1v = dyn_castNegVal(Op1)) {
298 match(Op1, m_NSWSub(m_Value(), m_Value())))
307 Value *Op1C = Op1;
[all...] |
| InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
38 if (Constant *CUI = dyn_cast<Constant>(Op1))
46 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
50 Op1->getName());
321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
326 if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1))
328 else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1))
331 COp1 = dyn_cast<ConstantInt>(Op1);
[all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineAndOrXor.cpp | [all...] |
| InstCombineCompares.cpp | [all...] |
| InstructionCombining.cpp | 202 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1));
235 if (Op1 && Op1->getOpcode() == Opcode) {
237 Value *B = Op1->getOperand(0);
238 Value *C = Op1->getOperand(1);
277 if (Op1 && Op1->getOpcode() == Opcode) {
279 Value *B = Op1->getOperand(0);
280 Value *C = Op1->getOperand(1);
298 if (Op0 && Op1 &
[all...] |
| InstCombineCalls.cpp | 479 static Value *SimplifyX86insertq(IntrinsicInst &II, Value *Op0, Value *Op1,
529 Builder.CreateBitCast(Op1, ShufTy),
536 Constant *C1 = dyn_cast<Constant>(Op1);
565 Value *Args[] = {Op0, Op1, CILength, CIIndex};
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 171 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
172 if (Op1->getOpcode() == OpcodeToExpand) {
174 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
208 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
230 if (Op1 && Op1->getOpcode() == Opcode) {
232 Value *B = Op1->getOperand(0);
233 Value *C = Op1->getOperand(1);
272 if (Op1 && Op1->getOpcode() == Opcode)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 51 SDValue Op1, SDValue Op2,
68 SDValue Op1, SDValue Op2,
84 SDValue Op1, SDValue Op2,
97 SDValue Op1, SDValue Op2,
136 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 205 const MachineOperand *Op1 = &MI1.getOperand(N1 + X86::AddrDisp);
207 if (!isIdenticalOp(*Op1, *Op2)) {
208 if (Op1->isImm() && Op2->isImm())
209 AddrDispShift = Op1->getImm() - Op2->getImm();
210 else if (Op1->isGlobal() && Op2->isGlobal() &&
211 Op1->getGlobal() == Op2->getGlobal())
212 AddrDispShift = Op1->getOffset() - Op2->getOffset();
|
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 672 MachineOperand &Op1 = MI->getOperand(1);
673 assert(Op0.isReg() && Op1.isImm());
674 uint64_t V = Op1.getImm();
700 MachineOperand &Op1 = MI->getOperand(1);
710 if (Op1.isImm()) {
712 .addImm(Op1.getImm());
713 } else if (Op1.isReg()) {
715 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg())
[all...] |
| HexagonExpandPredSpillCode.cpp | 102 MachineOperand &Op1 = MI->getOperand(1);
113 NewMI->addOperand(Op1);
145 MachineOperand &Op1 = MI->getOperand(1);
155 NewMI->addOperand(Op1);
187 MachineOperand &Op1 = MI->getOperand(1);
196 NewMI->addOperand(Op1);
224 MachineOperand &Op1 = MI->getOperand(1);
234 NewMI->addOperand(Op1);
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 157 const MCOperand Op1 = MI.getOperand(1);
158 assert(Op1.isReg() && "First operand is not register.");
159 Encoding = MRI.getEncodingValue(Op1.getReg());
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name);
85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name);
96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name);
382 Scatterer Op1 = scatter(&I, I.getOperand(1));
384 assert(Op1.size() == NumElems && "Mismatched binary operation");
388 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem],
401 Scatterer Op1 = scatter(&SI, SI.getOperand(1))
[all...] |
| CorrelatedValuePropagation.cpp | 195 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
196 if (!Op1) return false;
208 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C);
347 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
348 if (!Op1) return nullptr;
351 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 647 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
652 Ops.push_back(Op1);
[all...] |
| FastISel.h | 347 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
365 unsigned Op0, bool Op0IsKill, unsigned Op1,
401 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
407 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
432 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
| reduce.hpp | 157 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
162 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 735 SDValue Op1 = Op.getOperand(1);
739 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
772 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
779 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
781 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 414 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
415 // between the base and index. Try to fold Op1 into AM's displacement.
417 SDValue Op0, uint64_t Op1) {
419 int64_t TestDisp = AM.Disp + Op1;
441 SDValue Op1 = N.getOperand(1);
444 unsigned Op1Code = Op1->getOpcode();
447 return expandAdjDynAlloc(AM, IsBase, Op1);
452 return expandDisp(AM, IsBase, Op1,
456 cast<ConstantSDNode>(Op1)->getSExtValue());
458 if (IsBase && expandIndex(AM, Op0, Op1))
[all...] |
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
| reduce.hpp | 71 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
75 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
