| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 139 struct OpInfo
141 OpInfo *variants;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
162 inline const OpInfo& getOpInfo(const operation) const;
210 OpInfo opInfo[OP_LAST + 1];
213 const Target::OpInfo& Target::getOpInfo(const Instruction *insn) const
215 return opInfo[MIN2(insn->op, OP_LAST)];
218 const Target::OpInfo& Target::getOpInfo(const operation op) const
220 return opInfo[op]
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitCodes.h | 179 void Add(const BitCodeAbbrevOp &OpInfo) {
180 OperandList.push_back(OpInfo);
|
| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 171 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
173 unsigned MIOp = OpInfo.MIOperandNo;
174 Operands.emplace_back(OpInfo.PrinterMethodName, OpNo, MIOp, Modifier,
|
| AsmMatcherEmitter.cpp | [all...] |
| FixedLenDecoderEmitter.cpp | 451 const OperandInfo &OpInfo,
[all...] |
| InstrInfoEmitter.cpp | 58 const OperandInfoMapTy &OpInfo,
465 const OperandInfoMapTy &OpInfo,
546 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 149 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
165 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
167 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
540 if (OpInfo[i].isPredicate())
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.h | 347 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
349 if (OpInfo.RegClass == -1) {
351 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
355 return RI.getRegClass(OpInfo.RegClass)->getSize();
385 /// definition \p OpInfo. Note this does not attempt to validate constant bus
388 const MCOperandInfo &OpInfo,
394 const MCOperandInfo &OpInfo,
|
| SIInstrInfo.cpp | 923 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0))
[all...] |
| SIFoldOperands.cpp | 227 TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
286 UseDesc.OpInfo[UseOpIdx].RegClass == -1)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 80 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
203 int RCID = Desc.OpInfo[i].RegClass;
265 int RCID = Desc.OpInfo[OpNo].RegClass;
|
| /external/clang/lib/CodeGen/ |
| CGExprComplex.cpp | [all...] |
| CGExprScalar.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 125 TargetTransformInfo::OperandValueKind OpInfo =
130 OpInfo = TargetTransformInfo::OK_NonUniformConstantValue;
132 OpInfo = TargetTransformInfo::OK_UniformConstantValue;
135 return OpInfo;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 111 switch (MI.getDesc().OpInfo[i].RegClass) {
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
749 if (SkipPred && MCID.OpInfo[i].isPredicate())
782 if (MCID.OpInfo[i].isPredicate())
792 !MCID.OpInfo[i].isPredicate()) {
842 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
852 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 311 int RCID = Desc.OpInfo[OpNo].RegClass;
320 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
334 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
|
| TargetInstrInfo.cpp | 50 short RegClass = MCID.OpInfo[OpNum].RegClass;
51 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
284 if (MCID.OpInfo[i].isPredicate()) {
[all...] |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 271 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
