| /external/dhcpcd-6.8.2/crypt/ |
| sha256.c | 78 #define ROTR(x, n) ((x >> n) | (x << (32 - n)))
79 #define S0(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
80 #define S1(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
81 #define s0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3))
82 #define s1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10)
[all...] |
| /external/vboot_reference/firmware/2lib/ |
| 2sha256.c | 43 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
48 #define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
49 #define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
50 #define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
51 #define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)
[all...] |
| 2sha512.c | 43 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
48 #define SHA512_F1(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39))
49 #define SHA512_F2(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41))
50 #define SHA512_F3(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHFR(x, 7))
51 #define SHA512_F4(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHFR(x, 6)
[all...] |
| /external/vboot_reference/firmware/lib/cryptolib/ |
| sha256.c | 44 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
49 #define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
50 #define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
51 #define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
52 #define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)
[all...] |
| sha512.c | 44 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
49 #define SHA512_F1(x) (ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39))
50 #define SHA512_F2(x) (ROTR(x, 14) ^ ROTR(x, 18) ^ ROTR(x, 41))
51 #define SHA512_F3(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHFR(x, 7))
52 #define SHA512_F4(x) (ROTR(x, 19) ^ ROTR(x, 61) ^ SHFR(x, 6)
[all...] |
| /external/mmc-utils/3rdparty/hmac_sha/ |
| sha2.c | 47 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
52 #define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
53 #define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
54 #define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
55 #define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)
[all...] |
| /external/boringssl/src/crypto/sha/ |
| sha512.c | 361 #define ROTR(a, n) \
382 #define ROTR(a, n) \
389 #define ROTR(a, n) \
408 #define ROTR(a, n) _rotr64((a), n)
432 #ifndef ROTR
433 #define ROTR(x, s) (((x) >> s) | (x) << (64 - s))
436 #define Sigma0(x) (ROTR((x), 28) ^ ROTR((x), 34) ^ ROTR((x), 39))
437 #define Sigma1(x) (ROTR((x), 14) ^ ROTR((x), 18) ^ ROTR((x), 41)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| /external/boringssl/src/crypto/sha/asm/ |
| sha512-armv4.pl | 99 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
157 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
365 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
382 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| /external/pdfium/core/src/fdrm/crypto/ |
| fx_crypt_sha.cpp | 207 #define ROTR(x, n) (SHR(x, n) | (x << (32 - n)))
208 #define S0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3))
209 #define S1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10))
210 #define S2(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
211 #define S3(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)
[all...] |
| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV,
143 case ROTR:
146 TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
147 TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
148 TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
149 TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPS64Assembler.cpp | 389 case ROR: mMips->ROTR(tmpReg, amode.reg, amode.value); break;
512 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break;
539 case ROR: mMips->ROTR(Rd, amode.reg, amode.value); break;
[all...] |
| MIPSAssembler.cpp | 401 mMips->ROTR(tmpReg, amode.reg, amode.value);
512 mMips->ROTR(Rd, amode.reg, amode.value);
544 mMips->ROTR(Rd, amode.reg, amode.value);
[all...] |
| MIPSAssembler.h | 320 void ROTR(int Rd, int Rt, int shft); // mips32r2
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| rx-parse.y | 162 %token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD
735 | ROTR { sub_op = 4; } op_shift_rot
754 | ROTR '#' EXPR ',' REG
870 /* 000:SHLR, 001:SHAR, 010:SHLL, 011:-, 100:ROTR, 101:REVW, 110:ROTL, 111:REVL */
1072 OPC(ROTR),
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 147 setOperationAction(ISD::ROTR, MVT::i32, Expand);
148 setOperationAction(ISD::ROTR, MVT::i64, Expand);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 176 setOperationAction(ISD::ROTR, MVT::i64, Legal);
179 setOperationAction(ISD::ROTR, MVT::i64, Expand);
183 setOperationAction(ISD::ROTR, MVT::i32, Legal);
186 setOperationAction(ISD::ROTR, MVT::i32, Expand);
190 setOperationAction(ISD::ROTR, MVT::i16, Expand);
192 setOperationAction(ISD::ROTR, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 98 setOperationAction(ISD::ROTR, MVT::i8, Expand);
100 setOperationAction(ISD::ROTR, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 195 case ISD::ROTR: return "rotr";
|
| LegalizeVectorOps.cpp | 282 case ISD::ROTR:
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 132 setOperationAction(ISD::ROTR, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 151 // GPU doesn't have a rotl, rotr, or byteswap instruction
152 setOperationAction(ISD::ROTR, VT, Expand);
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| nds32-dis.c | 563 case ALU1 (ROTR):
|
