| /external/vogar/src/vogar/tasks/ |
| RmTask.java | 21 import vogar.commands.Rm;
24 private final Rm rm; field in class:RmTask
27 public RmTask(Rm rm, File file) {
28 super("rm " + file);
29 this.rm = rm;
34 rm.file(file);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| mul-overlap.l | 2 [^:]*:5: Rd and Rm should be different in mul
3 [^:]*:6: Rd and Rm should be different in mla
4 [^:]*:8: rdhi, rdlo and rm must all be different
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
82 virtual uint32_t reg_rrx(int Rm) = 0;
83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
87 // (immediate and Rm can be negative, which indicates U=0)
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
94 // (immediate and Rm can be negative, which indicates U=0)
97 virtual uint32_t reg_pre(int Rm, int W=0) = 0;
98 virtual uint32_t reg_post(int Rm) = 0;
129 int Rd, int Rm, int Rs, int Rn) = 0
[all...] |
| ARMAssembler.cpp | 229 int Rd, int Rm, int Rs, int Rn) {
230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
236 int Rd, int Rm, int Rs) {
237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
[all...] |
| ARMAssemblerProxy.cpp | 93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift)
95 return mTarget->reg_imm(Rm, type, shift);
98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm)
100 return mTarget->reg_rrx(Rm);
103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs)
105 return mTarget->reg_reg(Rm, type, Rs);
111 // (immediate and Rm can be negative, which indicates U=0)
122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W)
124 return mTarget->reg_scale_pre(Rm, type, shift, W);
127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, int type, uint32_t shift
[all...] |
| ARMAssembler.h | 70 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
71 virtual uint32_t reg_rrx(int Rm);
72 virtual uint32_t reg_reg(int Rm, int type, int Rs);
76 // (immediate and Rm can be negative, which indicates U=0)
79 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
80 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
83 // (immediate and Rm can be negative, which indicates U=0)
86 virtual uint32_t reg_pre(int Rm, int W=0);
87 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerProxy.h | 59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
60 virtual uint32_t reg_rrx(int Rm);
61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
65 // (immediate and Rm can be negative, which indicates U=0)
68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
72 // (immediate and Rm can be negative, which indicates U=0)
75 virtual uint32_t reg_pre(int Rm, int W=0);
76 virtual uint32_t reg_post(int Rm);
83 int Rd, int Rm, int Rs, int Rn)
[all...] |
| Arm64Assembler.h | 83 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
84 virtual uint32_t reg_rrx(int Rm);
85 virtual uint32_t reg_reg(int Rm, int type, int Rs);
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
94 virtual uint32_t reg_pre(int Rm, int W=0);
95 virtual uint32_t reg_post(int Rm);
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
106 int RdLo, int RdHi, int Rm, int Rs)
[all...] |
| Arm64Assembler.cpp | 376 uint32_t Rm;
382 Rm = mAddrMode.reg_imm_Rm;
388 Rm = Op2;
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
472 int Rm = mAddrMode.reg_imm_Rm;
474 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount)
[all...] |
| MIPS64Assembler.h | 73 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
74 virtual uint32_t reg_rrx(int Rm);
75 virtual uint32_t reg_reg(int Rm, int type, int Rs);
79 // (immediate and Rm can be negative, which indicates U=0)
82 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
83 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
86 // (immediate and Rm can be negative, which indicates U=0)
89 virtual uint32_t reg_pre(int Rm, int W=0);
90 virtual uint32_t reg_post(int Rm);
99 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPSAssembler.h | 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
69 virtual uint32_t reg_rrx(int Rm);
70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
74 // (immediate and Rm can be negative, which indicates U=0)
77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
81 // (immediate and Rm can be negative, which indicates U=0)
84 virtual uint32_t reg_pre(int Rm, int W=0);
85 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPS64Assembler.cpp | 227 uint32_t ArmToMips64Assembler::reg_imm(int Rm, int type, uint32_t shift)
229 amode.reg = Rm;
235 uint32_t ArmToMips64Assembler::reg_rrx(int Rm)
241 uint32_t ArmToMips64Assembler::reg_reg(int Rm, int type, int Rs)
249 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
270 uint32_t ArmToMips64Assembler::reg_scale_pre(int Rm, int type,
275 amode.reg = Rm;
282 uint32_t ArmToMips64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
288 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
308 uint32_t ArmToMips64Assembler::reg_pre(int Rm, int W
[all...] |
| MIPSAssembler.cpp | 234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
236 amode.reg = Rm;
242 uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
256 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
277 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
282 amode.reg = Rm;
289 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
295 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W
[all...] |
| /external/vogar/src/vogar/commands/ |
| Rm.java | 23 * A rm command.
25 public final class Rm {
28 public Rm(Log log) {
33 new Command(log, "rm", "-rf", file.getPath()).execute();
|
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /external/vogar/test/vogar/android/ |
| AbstractModeTest.java | 36 import vogar.commands.Rm;
51 protected Rm rm; field in class:AbstractModeTest
69 rm = new Rm(console);
83 run = new Run(vogar, false, console, mkdir, androidSdk, new Rm(console), target,
|
| /external/vogar/src/vogar/ |
| LocalTarget.java | 26 import vogar.commands.Rm;
39 private final Rm rm; field in class:LocalTarget
41 public LocalTarget(Log log, Mkdir mkdir, Rm rm) {
43 this.rm = rm;
62 @Override public void rm(File file) { method in class:LocalTarget
63 rm.file(file);
|
| OutcomeStore.java | 34 import vogar.commands.Rm;
51 private final Rm rm; field in class:OutcomeStore
57 public OutcomeStore(Log log, Mkdir mkdir, Rm rm, File resultsDir, boolean recordResults,
61 this.rm = rm;
173 rm.file(outcomeFiles[i]);
|
| Run.java | 39 import vogar.commands.Rm;
73 public final Rm rm; field in class:Run
118 Rm rm, Target target, File runnerDir)
140 this.rm = rm;
195 this.outcomeStore = new OutcomeStore(log, mkdir, rm, resultsDir, recordResults,
|
| /art/disassembler/ |
| disassembler_arm.cc | 154 explicit RmLslImm2(uint32_t instr) : imm2((instr >> 4) & 0x3), rm(instr & 0xf) {}
156 ArmRegister rm; member in struct:art::arm::RmLslImm2
159 os << r.rm;
278 // Show only Rd and Rm.
689 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
698 ArmRegister Rm(instr, 0);
782 args << Rm;
1682 args << rdn << ", " << rm; local
1695 args << DN_Rdn << ", " << rm; local
1706 args << DN_Rdn << ", " << rm; local
1716 args << N_Rn << ", " << rm; local
1724 args << rm; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
440 op2 = Rm;
441 regs[Rm] = test.RmValue;
445 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
446 regs[Rm] = test.RmValue;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
461 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
463 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break
[all...] |
| /system/core/libpixelflinger/tests/arch-mips64/assembler/ |
| mips64_assembler_test.cpp | 373 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2)
402 op2 = Rm;
403 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
407 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
408 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
418 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
419 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
423 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
424 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
425 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break
[all...] |
| /external/v8/src/arm64/ |
| disasm-arm64.h | 57 return (instr->Rm() == kZeroRegCode);
|
| /external/vixl/examples/ |
| non-const-visitor.h | 42 int rm = instr->Rm(); local
48 // Switch the bitfields for the `rn` and `rm` registers.
50 instr_bits |= (rn << Rm_offset) | (rm << Rn_offset);
|
