1 /* 2 * Copyright (C) 2015 The Android Open Source Project 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <stdio.h> 30 #include <stdlib.h> 31 #include <string.h> 32 #include <unistd.h> 33 #include <errno.h> 34 35 #include <sys/mman.h> 36 #include <cutils/ashmem.h> 37 #include <cutils/atomic.h> 38 #include <cutils/log.h> 39 40 #define __STDC_FORMAT_MACROS 41 #include <inttypes.h> 42 43 #include "codeflinger/ARMAssemblerInterface.h" 44 #include "codeflinger/MIPS64Assembler.h" 45 using namespace android; 46 47 #define TESTS_DATAOP_ENABLE 1 48 #define TESTS_DATATRANSFER_ENABLE 1 49 #define ASSEMBLY_SCRATCH_SIZE 4096 50 51 void *instrMem; 52 uint32_t instrMemSize = 128 * 1024; 53 char dataMem[8192]; 54 55 typedef void (*asm_function_t)(); 56 extern "C" void asm_mips_test_jacket(asm_function_t function, 57 int64_t regs[], int32_t flags[]); 58 59 #define MAX_32BIT (uint32_t)(((uint64_t)1 << 32) - 1) 60 #define MAX_64BIT ((uint64_t)0xFFFFFFFFFFFFFFFF) 61 const uint32_t NA = 0; 62 const uint32_t NUM_REGS = 32; 63 const uint32_t NUM_FLAGS = 16; 64 65 enum instr_t 66 { 67 INSTR_ADD, 68 INSTR_SUB, 69 INSTR_AND, 70 INSTR_ORR, 71 INSTR_RSB, 72 INSTR_BIC, 73 INSTR_CMP, 74 INSTR_MOV, 75 INSTR_MVN, 76 INSTR_MUL, 77 INSTR_MLA, 78 INSTR_SMULBB, 79 INSTR_SMULBT, 80 INSTR_SMULTB, 81 INSTR_SMULTT, 82 INSTR_SMULWB, 83 INSTR_SMULWT, 84 INSTR_SMLABB, 85 INSTR_UXTB16, 86 INSTR_UBFX, 87 INSTR_ADDR_ADD, 88 INSTR_ADDR_SUB, 89 INSTR_LDR, 90 INSTR_LDRB, 91 INSTR_LDRH, 92 INSTR_ADDR_LDR, 93 INSTR_LDM, 94 INSTR_STR, 95 INSTR_STRB, 96 INSTR_STRH, 97 INSTR_ADDR_STR, 98 INSTR_STM 99 }; 100 101 enum shift_t 102 { 103 SHIFT_LSL, 104 SHIFT_LSR, 105 SHIFT_ASR, 106 SHIFT_ROR, 107 SHIFT_NONE 108 }; 109 110 enum offset_t 111 { 112 REG_SCALE_OFFSET, 113 REG_OFFSET, 114 IMM8_OFFSET, 115 IMM12_OFFSET, 116 NO_OFFSET 117 }; 118 119 enum cond_t 120 { 121 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, 122 HS = CS, 123 LO = CC 124 }; 125 126 const char * cc_code[] = 127 { 128 "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 129 "HI", "LS","GE","LT", "GT", "LE", "AL", "NV" 130 }; 131 132 struct condTest_t 133 { 134 int mode; 135 int32_t Rcond1; 136 int32_t Rcond2; 137 uint64_t Rcond1Value; 138 uint64_t Rcond2Value; 139 }; 140 141 142 struct dataOpTest_t 143 { 144 uint32_t id; 145 instr_t op; 146 condTest_t preCond; 147 cond_t cond; 148 bool setFlags; 149 uint64_t RnValue; 150 uint64_t RsValue; 151 bool immediate; 152 uint32_t immValue; 153 uint64_t RmValue; 154 uint32_t shiftMode; 155 uint32_t shiftAmount; 156 uint64_t RdValue; 157 bool checkRd; 158 uint64_t postRdValue; 159 }; 160 161 struct dataTransferTest_t 162 { 163 uint32_t id; 164 instr_t op; 165 uint32_t preFlag; 166 cond_t cond; 167 bool setMem; 168 uint64_t memOffset; 169 uint64_t memValue; 170 uint64_t RnValue; 171 offset_t offsetType; 172 uint64_t RmValue; 173 uint32_t immValue; 174 bool writeBack; 175 bool preIndex; 176 bool postIndex; 177 uint64_t RdValue; 178 uint64_t postRdValue; 179 uint64_t postRnValue; 180 bool checkMem; 181 uint64_t postMemOffset; 182 uint32_t postMemLength; 183 uint64_t postMemValue; 184 }; 185 186 187 dataOpTest_t dataOpTests [] = 188 { 189 {0xA000,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,NA,NA,NA,NA,1,0}, 190 {0xA001,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,NA,NA,NA,NA,1,MAX_64BIT}, 191 {0xA002,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,NA,NA,NA,1,0}, 192 {0xA003,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT-1,NA,NA,NA,1,MAX_64BIT}, 193 {0xA004,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL, 0,NA,1,0}, 194 {0xA005,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000001}, 195 {0xA006,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,2}, 196 {0xA007,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,2}, 197 {0xA008,INSTR_ADD,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,1}, 198 {0xA009,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,0}, 199 {0xA010,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,0,0,0,NA,1,1}, 200 {0xA011,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,0,0,0,NA,1,0}, 201 {0xA012,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,0,0,NA,1,1}, 202 {0xA013,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT-1,0,0,NA,1,0}, 203 {0xA014,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,0,NA,1,1}, 204 {0xA015,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0}, 205 {0xA016,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,1}, 206 {0xA017,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1}, 207 {0xA018,INSTR_AND,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,0}, 208 {0xA019,INSTR_AND,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_ASR,31,NA,1,1}, 209 {0xA020,INSTR_ORR,{0,0,0,0,0},AL,0,3,NA,1,MAX_32BIT,0,0,0,NA,1,MAX_64BIT}, 210 {0xA021,INSTR_ORR,{0,0,0,0,0},AL,0,2,NA,1,MAX_32BIT-1,0,0,0,NA,1,MAX_64BIT-1}, 211 {0xA022,INSTR_ORR,{0,0,0,0,0},AL,0,3,NA,0,0,MAX_32BIT,0,0,NA,1,MAX_64BIT}, 212 {0xA023,INSTR_ORR,{0,0,0,0,0},AL,0,2,NA,0,0,MAX_32BIT-1,0,0,NA,1,MAX_64BIT-1}, 213 {0xA024,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,0,NA,1,MAX_64BIT}, 214 {0xA025,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000001}, 215 {0xA026,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,1}, 216 {0xA027,INSTR_ORR,{0,0,0,0,0},AL,0,0,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1}, 217 {0xA028,INSTR_ORR,{0,0,0,0,0},AL,0,0,NA,0,0,3,SHIFT_ASR,1,NA,1,1}, 218 {0xA029,INSTR_ORR,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,MAX_64BIT}, 219 {0xA030,INSTR_CMP,{0,0,0,0,0},AL,1,0x10000,NA,1,0x10000,0,0,0,NA,0,0}, 220 {0xA031,INSTR_MUL,{0,0,0,0,0},AL,0,0,0x10000,0,0,0x10000,0,0,NA,1,0}, 221 {0xA032,INSTR_MUL,{0,0,0,0,0},AL,0,0,0x1000,0,0,0x10000,0,0,NA,1,0x10000000}, 222 {0xA033,INSTR_MUL,{0,0,0,0,0},AL,0,0,MAX_32BIT,0,0,1,0,0,NA,1,MAX_64BIT}, 223 {0xA034,INSTR_MLA,{0,0,0,0,0},AL,0,0x10000,0x10000,0,0,0x10000,0,0,NA,1,0x10000}, 224 {0xA035,INSTR_MLA,{0,0,0,0,0},AL,0,0x10000,0x1000,0,0,0x10000,0,0,NA,1,0x10010000}, 225 {0xA036,INSTR_SUB,{1,R_v1,R_a6,2,4},MI,0,2,NA,0,NA,1,NA,NA,2,1,1}, 226 {0xA037,INSTR_SUB,{2,R_v1,R_a6,2,0},MI,0,2,NA,0,NA,1,NA,NA,2,1,2}, 227 {0xA038,INSTR_SUB,{1,R_v1,R_a6,4,2},GE,0,2,NA,1,1,NA,NA,NA,2,1,1}, 228 {0xA039,INSTR_SUB,{1,R_a5,R_a6,2,7},GE,0,2,NA,1,1,NA,NA,NA,2,1,2}, 229 {0xA040,INSTR_SUB,{1,R_a5,R_a6,1,1},HS,0,2,NA,1,1,NA,NA,NA,2,1,1}, 230 {0xA041,INSTR_SUB,{1,R_a5,R_a6,0,1},HS,0,2,NA,1,1,NA,NA,NA,2,1,2}, 231 {0xA042,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,1,1<< 16,0,0,0,NA,1,UINT64_C(1) -(1<<16)}, 232 {0xA043,INSTR_SUB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,1,1,0,0,0,NA,1,MAX_64BIT-1}, 233 {0xA044,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,1,1,0,0,0,NA,1,0}, 234 {0xA045,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1<<16,0,0,NA,1,UINT64_C(1) -(1<<16)}, 235 {0xA046,INSTR_SUB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,0,NA,1,0,0,NA,1,MAX_64BIT-1}, 236 {0xA047,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,0,0,NA,1,0}, 237 {0xA048,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,SHIFT_LSL,16,NA,1,UINT64_C(1) -(1<<16)}, 238 {0xA049,INSTR_SUB,{0,0,0,0,0},AL,0,0x80000001,NA,0,NA,MAX_32BIT,SHIFT_LSL,31,NA,1,1}, 239 {0xA050,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,3,SHIFT_LSR,1,NA,1,0}, 240 {0xA051,INSTR_SUB,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,SHIFT_LSR,31,NA,1,0}, 241 {0xA052,INSTR_RSB,{1,R_a5,R_a6,4,1},GE,0,2,NA,1,0,NA,NA,NA,2,1,UINT64_C(-2)}, 242 {0xA053,INSTR_RSB,{1,R_a5,R_a6,UINT64_C(-1),1},GE,0,2,NA,1,0,NA,NA,NA,2,1,2}, 243 {0xA054,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,1,1<<16,NA,NA,NA,NA,1,(1<<16)-1}, 244 {0xA055,INSTR_RSB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,1,1,NA,NA,NA,NA,1,UINT64_C(1)-MAX_64BIT}, 245 {0xA056,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,1,1,NA,NA,NA,NA,1,0}, 246 {0xA057,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1<<16,0,0,NA,1,(1<<16)-1}, 247 {0xA058,INSTR_RSB,{0,0,0,0,0},AL,0,MAX_32BIT,NA,0,NA,1,0,0,NA,1,UINT64_C(1)-MAX_64BIT}, 248 {0xA059,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,0,0,NA,1,0}, 249 {0xA060,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,1,SHIFT_LSL,16,NA,1,(1<<16)-1}, 250 {0xA061,INSTR_RSB,{0,0,0,0,0},AL,0,0x80000001,NA,0,NA,MAX_32BIT ,SHIFT_LSL,31,NA,1,UINT64_C(-1)}, 251 {0xA062,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,3,SHIFT_LSR,1,NA,1,0}, 252 {0xA063,INSTR_RSB,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,SHIFT_LSR,31,NA,1,0}, 253 {0xA064,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,1,0x80000001,NA,NA,NA,NA,1,0xFFFFFFFF80000001}, 254 {0xA065,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,0x80000001,0,0,NA,1,0xFFFFFFFF80000001}, 255 {0xA066,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,NA,1,MAX_64BIT-1}, 256 {0xA067,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000000}, 257 {0xA068,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_LSR,1,NA,1,1}, 258 {0xA069,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSR,31,NA,1,1}, 259 {0xA070,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_ASR,1,NA,1,1}, 260 {0xA071,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,MAX_64BIT ,SHIFT_ASR,31,NA,1,MAX_64BIT}, 261 {0xA072,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,3,SHIFT_ROR,1,NA,1,0xFFFFFFFF80000001}, 262 {0xA073,INSTR_MOV,{0,0,0,0,0},AL,0,NA,NA,0,0,0x80000001,SHIFT_ROR,31,NA,1,3}, 263 {0xA074,INSTR_MOV,{0,0,0,0,0},AL,1,NA,NA,0,0,MAX_64BIT -1,SHIFT_ASR,1,NA,1,MAX_64BIT}, 264 {0xA075,INSTR_MOV,{0,0,0,0,0},AL,1,NA,NA,0,0,3,SHIFT_ASR,1,NA,1,1}, 265 {0xA076,INSTR_MOV,{2,R_a5,R_a6,6,8},MI,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2}, 266 {0xA077,INSTR_MOV,{2,R_a5,R_a6,UINT64_C(-4),UINT64_C(-8)},MI,0,NA,NA,0,0,0x80000001,0,0,2,1,0xFFFFFFFF80000001}, 267 {0xA078,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},LT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2}, 268 {0xA079,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},LT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001}, 269 {0xA080,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-5)},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,MAX_64BIT-1}, 270 {0xA081,INSTR_MOV,{1,R_a5,R_a6,5,5},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,0xFFFFFFFF80000000}, 271 {0xA082,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,2}, 272 {0xA083,INSTR_MOV,{1,R_a5,R_a6,4,1},LE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,2}, 273 {0xA084,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},LE,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001}, 274 {0xA085,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},LE,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,31,2,1,0xFFFFFFFF80000000}, 275 {0xA086,INSTR_MOV,{1,R_a5,R_a6,1,1},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2}, 276 {0xA087,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-3)},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001}, 277 {0xA088,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),0},GT,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2}, 278 {0xA089,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),UINT64_C(-1)},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,2}, 279 {0xA090,INSTR_MOV,{1,R_a5,R_a6,6,1},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,0xFFFFFFFF80000001}, 280 {0xA091,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GT,0,NA,NA,0,0,0x80000001,0,0,2,1,2}, 281 {0xA092,INSTR_MOV,{1,R_a5,R_a6,1,1},GT,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,2}, 282 {0xA093,INSTR_MOV,{1,R_a5,R_a6,4,1},GT,0,NA,NA,0,0,MAX_32BIT,SHIFT_LSL,1,2,1,MAX_64BIT-1}, 283 {0xA094,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},GT,0,NA,NA,0,0,MAX_32BIT ,SHIFT_LSL,1,2,1,2}, 284 {0xA095,INSTR_MOV,{1,R_a5,R_a6,1,UINT64_C(-1)},HS,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,2}, 285 {0xA096,INSTR_MOV,{1,R_a5,R_a6,UINT64_C(-1),1},HS,0,NA,NA,1,0x80000001,NA,NA,NA,2,1,0xFFFFFFFF80000001}, 286 {0xA097,INSTR_MVN,{1,R_a5,R_a6,1,4},HS,0,NA,NA,1,MAX_32BIT-1,NA,NA,NA,2,1,2}, 287 {0xA098,INSTR_MVN,{1,R_a5,R_a6,UINT64_C(-1),1},HS,0,NA,NA,1,MAX_32BIT-1,NA,NA,NA,2,1,1}, 288 {0xA099,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,1,0,NA,NA,NA,2,1,MAX_64BIT}, 289 {0xA100,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,0,NA,MAX_32BIT-1,NA,0,2,1,1}, 290 {0xA101,INSTR_MVN,{0,0,0,0,0},AL,0,NA,NA,0,NA,0x80000001,NA,0,2,1,0x7FFFFFFE}, 291 {0xA102,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,NA,NA,NA,NA,1,0}, 292 {0xA103,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,NA,NA,NA,NA,1,1}, 293 {0xA104,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,0,0,NA,1,0}, 294 {0xA105,INSTR_BIC,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT-1,0,0,NA,1,1}, 295 {0xA106,INSTR_BIC,{0,0,0,0,0},AL,0,0xF0,NA,0,0,3,SHIFT_ASR,1,NA,1,0xF0}, 296 {0xA107,INSTR_BIC,{0,0,0,0,0},AL,0,0xF0,NA,0,0,MAX_64BIT,SHIFT_ASR,31,NA,1,0}, 297 {0xA108,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 298 {0xA109,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00000FFF}, 299 {0xA110,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 300 {0xA111,INSTR_SMULBB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,1}, 301 {0xA112,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 302 {0xA113,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00000FFF}, 303 {0xA114,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 304 {0xA115,INSTR_SMULBT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFABCDFFFF,NA,NA,NA,1,1}, 305 {0xA116,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 306 {0xA117,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF}, 307 {0xA118,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 308 {0xA119,INSTR_SMULTB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,1}, 309 {0xA120,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 310 {0xA121,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF}, 311 {0xA122,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 312 {0xA123,INSTR_SMULTT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,1}, 313 {0xA124,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE}, 314 {0xA125,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF}, 315 {0xA126,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 316 {0xA127,INSTR_SMULWB,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0}, 317 {0xA128,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0x000000000001ABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE}, 318 {0xA129,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0x000000000FFFABCD,NA,NA,NA,1,0x00000FFF}, 319 {0xA130,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0x000000000001ABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0xFFFFFFFFFFFFFFFF}, 320 {0xA131,INSTR_SMULWT,{0,0,0,0,0},AL,0,NA,0xFFFFFFFFFFFFABCD,0,NA,0xFFFFFFFFFFFFABCD,NA,NA,NA,1,0}, 321 {0xA132,INSTR_SMLABB,{0,0,0,0,0},AL,0,1,0xFFFFFFFFABCDFFFF,0,NA,0xFFFFFFFFABCD0001,NA,NA,NA,1,0}, 322 {0xA133,INSTR_SMLABB,{0,0,0,0,0},AL,0,1,0xFFFFFFFFABCD0001,0,NA,0xFFFFFFFFABCD0FFF,NA,NA,NA,1,0x00001000}, 323 {0xA134,INSTR_SMLABB,{0,0,0,0,0},AL,0,0xFFFFFFFFFFFFFFFF,0xFFFFFFFFABCD0001,0,NA,0xABCDFFFF,NA,NA,NA,1,0xFFFFFFFFFFFFFFFE}, 324 {0xA135,INSTR_SMLABB,{0,0,0,0,0},AL,0,0xFFFFFFFFFFFFFFFF,0xFFFFFFFFABCDFFFF,0,NA,0xABCDFFFF,NA,NA,NA,1,0}, 325 {0xA136,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,0,NA,1,0x00CD0001}, 326 {0xA137,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,1,NA,1,0x00AB00EF}, 327 {0xA138,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,2,NA,1,0x000100CD}, 328 {0xA139,INSTR_UXTB16,{0,0,0,0,0},AL,0,NA,NA,0,NA,0xABCDEF01,SHIFT_ROR,3,NA,1,0x00EF00AB}, 329 {0xA140,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x1,SHIFT_LSL,1,NA,1,0xD00000001}, 330 {0xA141,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0x01,NA,0,NA,0x1,SHIFT_LSL,2,NA,1,0x5}, 331 {0xA142,INSTR_ADDR_ADD,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x1,NA,0,NA,1,0xD00000000}, 332 {0xA143,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,0xD00000001,NA,0,NA,0x010000,SHIFT_LSR,15,NA,1,0xCFFFFFFFF}, 333 {0xA144,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,0xCFFFFFFFF,NA,0,NA,0x020000,SHIFT_LSR,15,NA,1,0xCFFFFFFFB}, 334 {0xA145,INSTR_ADDR_SUB,{0,0,0,0,0},AL,0,3,NA,0,NA,0x010000,SHIFT_LSR,15,NA,1,1}, 335 }; 336 337 dataTransferTest_t dataTransferTests [] = 338 { 339 {0xB000,INSTR_LDR,AL,AL,1,24,0xABCDEF0123456789,0,REG_SCALE_OFFSET,24,NA,NA,NA,NA,NA,0x23456789,0,0,NA,NA,NA}, 340 {0xB001,INSTR_LDR,AL,AL,1,0,0xABCDEF0123456789,0,IMM12_OFFSET,NA,4,1,0,1,NA,0x23456789,4,0,NA,NA,NA}, 341 {0xB002,INSTR_LDR,AL,AL,1,0,0xABCDEF0123456789,0,NO_OFFSET,NA,NA,0,0,0,NA,0x23456789,0,0,NA,NA,NA}, 342 {0xB003,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,0,REG_SCALE_OFFSET,4064,NA,NA,NA,NA,NA,0x89,0,0,NA,NA,NA}, 343 {0xB004,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,0,0,1,0,NA,0x67,4065,0,NA,NA,NA}, 344 {0xB005,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,1,0,1,0,NA,0x45,4065,0,NA,NA,NA}, 345 {0xB006,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,2,0,1,0,NA,0x23,4065,0,NA,NA,NA}, 346 {0xB007,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,4065,IMM12_OFFSET,NA,1,1,0,1,NA,0x67,4066,0,NA,NA,NA}, 347 {0xB008,INSTR_LDRB,AL,AL,1,4064,0xABCDEF0123456789,0,NO_OFFSET,NA,NA,0,0,0,NA,0x89,0,0,NA,NA,NA}, 348 {0xB009,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,0,IMM8_OFFSET,NA,2,1,0,1,NA,0x6789,2,0,NA,NA,NA}, 349 {0xB010,INSTR_LDRH,AL,AL,1,4064,0xABCDEF0123456789,0,REG_OFFSET,4064,0,0,1,0,NA,0x6789,0,0,NA,NA,NA}, 350 {0xB011,INSTR_LDRH,AL,AL,1,4064,0xABCDEF0123456789,0,REG_OFFSET,4066,0,0,1,0,NA,0x2345,0,0,NA,NA,NA}, 351 {0xB012,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,0,NO_OFFSET,NA,0,0,0,0,NA,0x6789,0,0,NA,NA,NA}, 352 {0xB013,INSTR_LDRH,AL,AL,1,0,0xABCDEF0123456789,2,NO_OFFSET,NA,0,0,0,0,NA,0x2345,2,0,NA,NA,NA}, 353 {0xB014,INSTR_STR,AL,AL,1,2,0xDEADBEEFDEADBEEF,4,IMM12_OFFSET,NA,4,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,8,1,2,8,0xDEAD23456789BEEF}, 354 {0xB015,INSTR_STR,AL,AL,1,2,0xDEADBEEFDEADBEEF,4,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,4,1,2,8,0xDEAD23456789BEEF}, 355 {0xB016,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,0,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDEAD89EF}, 356 {0xB017,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,1,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDE89BEEF}, 357 {0xB018,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,2,0,1,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEF89ADBEEF}, 358 {0xB019,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,IMM12_OFFSET,NA,4,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,5,1,0,8,0xDEADBEEFDEAD89EF}, 359 {0xB020,INSTR_STRB,AL,AL,1,0,0xDEADBEEFDEADBEEF,1,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,1,1,0,8,0xDEADBEEFDEAD89EF}, 360 {0xB021,INSTR_STRH,AL,AL,1,4066,0xDEADBEEFDEADBEEF,4070,IMM8_OFFSET,NA,2,1,0,1,0xABCDEF0123456789,0xABCDEF0123456789,4072,1,4066,8,0xDEAD6789DEADBEEF}, 361 {0xB022,INSTR_STRH,AL,AL,1,4066,0xDEADBEEFDEADBEEF,4070,NO_OFFSET,NA,NA,0,0,0,0xABCDEF0123456789,0xABCDEF0123456789,4070,1,4066,8,0xDEAD6789DEADBEEF}, 362 }; 363 364 365 void flushcache() 366 { 367 const long base = long(instrMem); 368 const long curr = base + long(instrMemSize); 369 __builtin___clear_cache((char*)base, (char*)curr); 370 } 371 372 void dataOpTest(dataOpTest_t test, ArmToMips64Assembler *a64asm, uint32_t Rd = R_v1, 373 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2) 374 { 375 int64_t regs[NUM_REGS] = {0}; 376 int32_t flags[NUM_FLAGS] = {0}; 377 int64_t savedRegs[NUM_REGS] = {0}; 378 uint32_t i; 379 uint32_t op2; 380 381 for(i = 0; i < NUM_REGS; ++i) 382 { 383 regs[i] = i; 384 } 385 386 regs[Rd] = test.RdValue; 387 regs[Rn] = test.RnValue; 388 regs[Rs] = test.RsValue; 389 a64asm->reset(); 390 if (test.preCond.mode) { 391 a64asm->set_condition(test.preCond.mode, test.preCond.Rcond1, test.preCond.Rcond2); 392 regs[test.preCond.Rcond1] = test.preCond.Rcond1Value; 393 regs[test.preCond.Rcond2] = test.preCond.Rcond2Value; 394 } 395 a64asm->prolog(); 396 if(test.immediate == true) 397 { 398 op2 = a64asm->imm(test.immValue); 399 } 400 else if(test.immediate == false && test.shiftAmount == 0) 401 { 402 op2 = Rm; 403 regs[Rm] = (int64_t)((int32_t)(test.RmValue)); 404 } 405 else 406 { 407 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount); 408 regs[Rm] = (int64_t)((int32_t)(test.RmValue)); 409 } 410 switch(test.op) 411 { 412 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break; 413 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break; 414 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break; 415 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break; 416 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break; 417 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break; 418 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break; 419 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; 420 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break; 421 case INSTR_MOV: a64asm->MOV(test.cond, test.setFlags,Rd,op2); break; 422 case INSTR_MVN: a64asm->MVN(test.cond, test.setFlags,Rd,op2); break; 423 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break; 424 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break; 425 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break; 426 case INSTR_SMULTT:a64asm->SMULTT(test.cond, Rd,Rm,Rs); break; 427 case INSTR_SMULWB:a64asm->SMULWB(test.cond, Rd,Rm,Rs); break; 428 case INSTR_SMULWT:a64asm->SMULWT(test.cond, Rd,Rm,Rs); break; 429 case INSTR_SMLABB:a64asm->SMLABB(test.cond, Rd,Rm,Rs,Rn); break; 430 case INSTR_UXTB16:a64asm->UXTB16(test.cond, Rd,Rm,test.shiftAmount); break; 431 case INSTR_ADDR_ADD: a64asm->ADDR_ADD(test.cond, test.setFlags, Rd,Rn,op2); break; 432 case INSTR_ADDR_SUB: a64asm->ADDR_SUB(test.cond, test.setFlags, Rd,Rn,op2); break; 433 default: printf("Error"); return; 434 } 435 a64asm->epilog(0); 436 a64asm->fix_branches(); 437 flushcache(); 438 439 asm_function_t asm_function = (asm_function_t)(instrMem); 440 441 for(i = 0; i < NUM_REGS; ++i) 442 savedRegs[i] = regs[i]; 443 444 asm_mips_test_jacket(asm_function, regs, flags); 445 446 /* Check if all regs except Rd is same */ 447 for(i = 0; i < NUM_REGS; ++i) 448 { 449 if((i == Rd) || i == 2) continue; 450 if(regs[i] != savedRegs[i]) 451 { 452 printf("Test %x failed Reg(%d) tampered Expected(0x%" PRIx64 ")," 453 "Actual(0x%" PRIx64 ") t\n", test.id, i, savedRegs[i], 454 regs[i]); 455 exit(0); 456 return; 457 } 458 } 459 460 if(test.checkRd == 1 && regs[Rd] != test.postRdValue) 461 { 462 printf("Test %x failed, Expected(%" PRIx64 "), Actual(%" PRIx64 ")\n", 463 test.id, test.postRdValue, regs[Rd]); 464 exit(0); 465 } 466 else 467 { 468 printf("Test %x passed\n", test.id); 469 } 470 } 471 472 473 void dataTransferTest(dataTransferTest_t test, ARMAssemblerInterface *a64asm, 474 uint32_t Rd = R_v1, uint32_t Rn = R_t0,uint32_t Rm = R_t1) 475 { 476 int64_t regs[NUM_REGS] = {0}; 477 int64_t savedRegs[NUM_REGS] = {0}; 478 int32_t flags[NUM_FLAGS] = {0}; 479 uint32_t i; 480 for(i = 0; i < NUM_REGS; ++i) 481 { 482 regs[i] = i; 483 } 484 485 uint32_t op2; 486 487 regs[Rd] = test.RdValue; 488 regs[Rn] = (uint64_t)(&dataMem[test.RnValue]); 489 regs[Rm] = test.RmValue; 490 flags[test.preFlag] = 1; 491 492 if(test.setMem == true) 493 { 494 unsigned char *mem = (unsigned char *)&dataMem[test.memOffset]; 495 uint64_t value = test.memValue; 496 for(int j = 0; j < 8; ++j) 497 { 498 mem[j] = value & 0x00FF; 499 value >>= 8; 500 } 501 } 502 a64asm->reset(); 503 a64asm->prolog(); 504 if(test.offsetType == REG_SCALE_OFFSET) 505 { 506 op2 = a64asm->reg_scale_pre(Rm); 507 } 508 else if(test.offsetType == REG_OFFSET) 509 { 510 op2 = a64asm->reg_pre(Rm); 511 } 512 else if(test.offsetType == IMM12_OFFSET && test.preIndex == true) 513 { 514 op2 = a64asm->immed12_pre(test.immValue, test.writeBack); 515 } 516 else if(test.offsetType == IMM12_OFFSET && test.postIndex == true) 517 { 518 op2 = a64asm->immed12_post(test.immValue); 519 } 520 else if(test.offsetType == IMM8_OFFSET && test.preIndex == true) 521 { 522 op2 = a64asm->immed8_pre(test.immValue, test.writeBack); 523 } 524 else if(test.offsetType == IMM8_OFFSET && test.postIndex == true) 525 { 526 op2 = a64asm->immed8_post(test.immValue); 527 } 528 else if(test.offsetType == NO_OFFSET) 529 { 530 op2 = a64asm->__immed12_pre(0); 531 } 532 else 533 { 534 printf("Error - Unknown offset\n"); return; 535 } 536 537 switch(test.op) 538 { 539 case INSTR_LDR: a64asm->LDR(test.cond, Rd,Rn,op2); break; 540 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break; 541 case INSTR_LDRH: a64asm->LDRH(test.cond, Rd,Rn,op2); break; 542 case INSTR_ADDR_LDR: a64asm->ADDR_LDR(test.cond, Rd,Rn,op2); break; 543 case INSTR_STR: a64asm->STR(test.cond, Rd,Rn,op2); break; 544 case INSTR_STRB: a64asm->STRB(test.cond, Rd,Rn,op2); break; 545 case INSTR_STRH: a64asm->STRH(test.cond, Rd,Rn,op2); break; 546 case INSTR_ADDR_STR: a64asm->ADDR_STR(test.cond, Rd,Rn,op2); break; 547 default: printf("Error"); return; 548 } 549 a64asm->epilog(0); 550 flushcache(); 551 552 asm_function_t asm_function = (asm_function_t)(instrMem); 553 554 for(i = 0; i < NUM_REGS; ++i) 555 savedRegs[i] = regs[i]; 556 557 asm_mips_test_jacket(asm_function, regs, flags); 558 559 /* Check if all regs except Rd/Rn are same */ 560 for(i = 0; i < NUM_REGS; ++i) 561 { 562 if(i == Rd || i == Rn || i == R_v0) continue; 563 564 if(regs[i] != savedRegs[i]) 565 { 566 printf("Test %x failed Reg(%d) tampered" 567 " Expected(0x%" PRIx64 "), Actual(0x%" PRIx64 ") t\n", 568 test.id, i, savedRegs[i], regs[i]); 569 return; 570 } 571 } 572 573 if((uint64_t)regs[Rd] != test.postRdValue) 574 { 575 printf("Test %x failed, " 576 "Expected in Rd(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n", 577 test.id, test.postRdValue, regs[Rd]); 578 } 579 else if((uint64_t)regs[Rn] != (uint64_t)(&dataMem[test.postRnValue])) 580 { 581 printf("Test %x failed, " 582 "Expected in Rn(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n", 583 test.id, test.postRnValue, regs[Rn] - (uint64_t)dataMem); 584 } 585 else if(test.checkMem == true) 586 { 587 unsigned char *addr = (unsigned char *)&dataMem[test.postMemOffset]; 588 uint64_t value; 589 value = 0; 590 for(uint32_t j = 0; j < test.postMemLength; ++j) 591 value = (value << 8) | addr[test.postMemLength-j-1]; 592 if(value != test.postMemValue) 593 { 594 printf("Test %x failed, " 595 "Expected in Mem(0x%" PRIx64 "), Actual(0x%" PRIx64 ")\n", 596 test.id, test.postMemValue, value); 597 } 598 else 599 { 600 printf("Test %x passed\n", test.id); 601 } 602 } 603 else 604 { 605 printf("Test %x passed\n", test.id); 606 } 607 } 608 609 int main(void) 610 { 611 uint32_t i; 612 613 /* Allocate memory to store instructions generated by ArmToArm64Assembler */ 614 { 615 int fd = ashmem_create_region("code cache", instrMemSize); 616 if(fd < 0) { 617 printf("IF < 0\n"); 618 printf("Creating code cache, ashmem_create_region " 619 "failed with error '%s'", strerror(errno)); 620 } 621 instrMem = mmap(NULL, instrMemSize, 622 PROT_READ | PROT_WRITE | PROT_EXEC, 623 MAP_PRIVATE, fd, 0); 624 } 625 626 ArmToMips64Assembler a64asm(instrMem); 627 628 if(TESTS_DATAOP_ENABLE) 629 { 630 printf("Running data processing tests\n"); 631 for(i = 0; i < sizeof(dataOpTests)/sizeof(dataOpTest_t); ++i) { 632 dataOpTest(dataOpTests[i], &a64asm); 633 } 634 } 635 636 if(TESTS_DATATRANSFER_ENABLE) 637 { 638 printf("Running data transfer tests\n"); 639 for(i = 0; i < sizeof(dataTransferTests)/sizeof(dataTransferTest_t); ++i) 640 dataTransferTest(dataTransferTests[i], &a64asm); 641 } 642 643 return 0; 644 } 645
