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  /external/clang/test/CXX/concepts-ts/dcl.dcl/dcl.spec/dcl.spec.concept/
p2.cpp 5 template<typename T> concept constexpr bool VCC = true; // expected-error {{variable concept cannot be declared 'constexpr'}}
  /external/llvm/lib/Target/AMDGPU/
SIShrinkInstructions.cpp 94 // is vcc. We should handle this the same way we handle vopc, by addding
253 // VOPC instructions can only write to the VCC register. We can't
254 // force them to use VCC here, because this is only one register and
256 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
258 // So, instead of forcing the instruction to write to VCC, we provide
259 // a hint to the register allocator to use VCC and then we we will run
260 // this pass again after RA and shrink it if it outputs to VCC.
261 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
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SILowerControlFlow.cpp 19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
187 unsigned Vcc = MI.getOperand(1).getReg();
190 .addReg(Vcc);
239 unsigned Vcc = MI.getOperand(1).getReg();
243 .addReg(Vcc)
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AMDGPUAsmPrinter.cpp 357 case AMDGPU::VCC:
SIRegisterInfo.cpp 45 // 98/99 need to be reserved for flat_scr, and 100/101 for vcc. This is the
62 // Next register before reservations for flat_scr and vcc.
79 // will physically contain VCC.
86 // for VCC/FLAT_SCR.
95 // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
343 // VCC, but we're unlikely to see VMEM use VCC.
509 case AMDGPU::VCC:
513 default: llvm_unreachable("Invalid SubIdx for VCC");
SIInstrInfo.cpp 373 if (DestReg == AMDGPU::VCC) {
375 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
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  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUAsmPrinter.cpp 80 if (reg == AMDGPU::VCC) {
SIGenRegisterInfo.pl 90 def VCC : SIReg<"VCC">;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
273 #Add VCC to SReg_64
275 push (@registers, 'VCC')
SIISelLowering.cpp 208 AMDGPU::VCC)
239 AMDGPU::VCC)
245 .addReg(AMDGPU::VCC)
286 /// VCC register. In the VALU context, VCC is a one bit register, but in the
287 /// SALU context the VCC is a 64-bit register (1-bit per thread). Since only
288 /// the SALU can perform operations on the VCC register, we need to promote
  /external/llvm/lib/Target/AMDGPU/InstPrinter/
AMDGPUInstPrinter.cpp 133 case AMDGPU::VCC:
134 O << "vcc";
  /external/clang/unittests/AST/
CommentParser.cpp     [all...]
  /external/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 506 .Case("vcc", AMDGPU::VCC)
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