| /external/llvm/lib/Target/WebAssembly/InstPrinter/ |
| WebAssemblyInstPrinter.cpp | 88 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs())
95 if (OpNo < MII.get(MI->getOpcode()).getNumDefs())
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 91 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
|
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 330 Offset < PageSize && MI->getDesc().getNumDefs() <= 1 &&
356 unsigned NumDefs = LoadMI->getDesc().getNumDefs();
|
| ExecutionDepsFix.cpp | 513 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
583 for (unsigned i = mi->getDesc().getNumDefs(),
593 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
612 for (unsigned i = mi->getDesc().getNumDefs(),
|
| PeepholeOptimizer.cpp | 375 assert(DefIdx < Def->getDesc().getNumDefs() &&
[all...] |
| MachineCSE.cpp | 533 unsigned NumDefs = MI->getDesc().getNumDefs() +
|
| MachineLICM.cpp | [all...] |
| TargetInstrInfo.cpp | 126 bool HasDef = MCID.getNumDefs();
247 unsigned CommutableOpIdx1 = MCID.getNumDefs();
[all...] |
| MachineVerifier.cpp | 835 unsigned NumDefs = MCID.getNumDefs();
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| RegAllocFast.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| ScheduleDAGSDNodes.cpp | 127 if (ResNo >= II.getNumDefs() &&
128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
451 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
[all...] |
| InstrEmitter.cpp | 134 if (i+II.getNumDefs() < II.getNumOperands()) {
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
215 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
751 unsigned NumDefs = II.getNumDefs();
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| ResourcePriorityQueue.cpp | 557 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs());
|
| ScheduleDAGFast.cpp | 442 NumRes = MCID.getNumDefs();
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 322 operands_begin() + getDesc().getNumDefs());
327 operands_begin() + getDesc().getNumDefs());
332 return make_range(operands_begin() + getDesc().getNumDefs(),
337 return make_range(operands_begin() + getDesc().getNumDefs(),
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 63 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
117 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
200 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 191 unsigned getNumDefs() const { return NumDefs; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 293 if (II.getNumDefs() >= 1) {
318 if (II.getNumDefs() >= 1) {
348 if (II.getNumDefs() >= 1) {
376 if (II.getNumDefs() >= 1) {
404 if (II.getNumDefs() >= 1) {
428 if (II.getNumDefs() >= 1) {
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 188 unsigned OpIdx = Desc.getNumDefs() + OpNo;
[all...] |
