/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 149 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 159 { ISD::SHL, MVT::v4i64, 1 }, 160 { ISD::SRL, MVT::v4i64, 1 }, 200 { ISD::SHL, MVT::v4i64, 2 }, 201 { ISD::SRL, MVT::v4i64, 4 }, 202 { ISD::SRA, MVT::v4i64, 4 }, 221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 227 { ISD::SDIV, MVT::v4i64, 4*20 }, 231 { ISD::UDIV, MVT::v4i64, 4*20 } [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineValueType.h | 97 v4i64 = 47, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType 252 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); 344 case v4i64: 400 case v4i64: 486 case v4i64: 628 if (NumElements == 4) return MVT::v4i64;
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/external/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 394 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
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/external/llvm/lib/IR/ |
ValueTypes.cpp | 174 case MVT::v4i64: return "v4i64"; 252 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
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/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 83 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 87 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 88 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 277 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
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ARMISelDAGToDAG.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
X86InstComments.cpp | 88 DstVT = MVT::v4i64; 113 DstVT = MVT::v4i64; 126 DstVT = MVT::v4i64; 631 // For instruction comments purpose, assume the 256-bit vector is v4i64. 633 DecodeVPERM2X128Mask(MVT::v4i64,
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/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 107 case MVT::v4i64: return "MVT::v4i64";
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/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 191 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 147 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand); [all...] |