/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 149 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 154 { ISD::SHL, MVT::v8i32, 1 }, 155 { ISD::SRL, MVT::v8i32, 1 }, 156 { ISD::SRA, MVT::v8i32, 1 }, 197 { ISD::SHL, MVT::v8i32, 2 }, 198 { ISD::SRL, MVT::v8i32, 4 }, 199 { ISD::SRA, MVT::v8i32, 4 }, 226 { ISD::SDIV, MVT::v8i32, 8*20 } [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineValueType.h | 90 v8i32 = 41, // 8 x i32 enumerator in enum:llvm::MVT::SimpleValueType 252 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); 338 case v8i32: 391 case v8i32: 485 case v8i32: 620 if (NumElements == 8) return MVT::v8i32;
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/external/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 392 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
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/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 89 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 90 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 100 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 121 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
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/external/llvm/lib/IR/ |
ValueTypes.cpp | 168 case MVT::v8i32: return "v8i32"; 246 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8);
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86InstComments.cpp | 76 DstVT = MVT::v8i32; 101 DstVT = MVT::v8i32;
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/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 101 case MVT::v8i32: return "MVT::v8i32";
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIISelLowering.cpp | 38 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
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/external/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); 69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); 88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); 91 setOperationAction(ISD::STORE, MVT::v8i32, Custom); 167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand); 205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { [all...] |
AMDGPUISelLowering.cpp | 120 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); 160 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); 173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 191 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || 257 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) { [all...] |