| /external/llvm/examples/Kaleidoscope/Orc/initial/ |
| toy.cpp | 142 UnaryExprAST(char Opcode, std::unique_ptr<ExprAST> Operand)
143 : Opcode(std::move(Opcode)), Operand(std::move(Operand)) {}
147 char Opcode;
770 std::string FnName = MakeLegalFunctionName(std::string("unary")+Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/Orc/lazy_codegen/ |
| toy.cpp | 142 UnaryExprAST(char Opcode, std::unique_ptr<ExprAST> Operand)
143 : Opcode(std::move(Opcode)), Operand(std::move(Operand)) {}
147 char Opcode;
770 std::string FnName = MakeLegalFunctionName(std::string("unary")+Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/Orc/lazy_irgen/ |
| toy.cpp | 142 UnaryExprAST(char Opcode, std::unique_ptr<ExprAST> Operand)
143 : Opcode(std::move(Opcode)), Operand(std::move(Operand)) {}
147 char Opcode;
770 std::string FnName = MakeLegalFunctionName(std::string("unary")+Opcode);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 135 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
139 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
153 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
154 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
176 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
177 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
200 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)Opc;
201 assert(Instruction::isAssociative(Opcode) && "Not an associative operation!");
211 if (Op0 && Op0->getOpcode() == Opcode) {
217 if (Value *V = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse))
[all...] |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/Object/ |
| MachOObjectFile.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 221 // opcode and that it has a immediate integer right operand.
252 // which lists [imm] as the list of opcode it's interested in, however
254 // here because the ComplexPattern opcode list is only used in
255 // root-level opcode matching.
282 // which lists [imm] as the list of opcode it's interested in, however
284 // here because the ComplexPattern opcode list is only used in
285 // root-level opcode matching.
774 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 142 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
[all...] |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 243 /// opcode.
[all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 96 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
98 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
255 unsigned Opcode,
266 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
286 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
308 unsigned Opcode,
320 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
343 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
376 unsigned Opcode = 0;
384 // Figure out the opcode
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 250 llvm_unreachable("unexpected opcode");
410 unsigned Opcode = Instruction::UserOp1;
416 Opcode = I->getOpcode();
420 Opcode = C->getOpcode();
423 switch (Opcode) {
492 unsigned Opcode = Instruction::UserOp1;
498 Opcode = I->getOpcode();
502 Opcode = C->getOpcode();
506 switch (Opcode) {
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 276 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
828 int Opcode = Inst.getOpcode();
829 switch (Opcode) {
835 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
838 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
914 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
928 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
942 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 306 unsigned Opcode = Instruction::UserOp1;
312 Opcode = I->getOpcode();
316 Opcode = C->getOpcode();
320 switch (Opcode) {
550 // Get the RR opcode corresponding to the RI one. FIXME: It would be
554 default: llvm_unreachable("Unexpected opcode!");
686 // Get the RR opcode corresponding to the RI one. FIXME: It would be
690 default: llvm_unreachable("Unexpected opcode!");
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 45 getTargetNodeName(unsigned Opcode) const
47 switch ((XCoreISD::NodeType)Opcode)
751 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
754 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
758 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 358 unsigned Opcode = I->getOpcode();
360 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
383 if (Opcode == Instruction::FSub)
[all...] |
| InstCombineAndOrXor.cpp | 67 /// This is the complement of getICmpCode, which turns an opcode and two
79 /// This is the complement of getFCmpCode, which turns an opcode and two
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 62 CheckOpcode, // Fail if not opcode.
63 SwitchOpcode, // Dispatch based on opcode.
479 /// specified opcode, if not it fails to match.
481 const SDNodeInfo &Opcode;
483 CheckOpcodeMatcher(const SDNodeInfo &opcode)
484 : Matcher(CheckOpcode), Opcode(opcode) {}
486 const SDNodeInfo &getOpcode() const { return Opcode; }
501 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
502 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 340 gl_inst_opcode Opcode;
439 _mesa_num_inst_src_regs(gl_inst_opcode opcode);
442 _mesa_num_inst_dst_regs(gl_inst_opcode opcode);
445 _mesa_is_tex_instruction(gl_inst_opcode opcode);
451 _mesa_opcode_string(gl_inst_opcode opcode);
|
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Opcode.java | 19 public enum Opcode {
277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) {
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
|
| /dalvik/libdex/ |
| DexOpcodes.h | 18 * Dalvik opcode information.
21 * automatically by the opcode-gen tool. Any edits to the generated
24 * See the file opcode-gen/README.txt for information about updating
34 * kMaxOpcodeValue: the highest possible raw (unpacked) opcode value
36 * kNumPackedOpcodes: the highest possible packed opcode value of a
37 * valid Dalvik opcode, plus one
42 // BEGIN(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
45 // END(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
58 * associated with each is the corresponding packed opcode number.
59 * This is different than the opcode value from the Dalvik bytecod
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 148 module Opcode = struct
283 | Instruction of Opcode.t
451 external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode"
[all...] |
