| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_pair.h | 72 unsigned int Opcode:8;
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| radeon_program.h | 65 rc_presubtract_op Opcode;
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8;
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| /external/mesa3d/src/mesa/main/ |
| atifragshader.h | 24 GLenum opcode; member in struct:ati_fs_opcode_st
53 GLenum Opcode[2];
62 GLenum Opcode;
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| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
156 MCInst() : Opcode(0) {}
158 void setOpcode(unsigned Op) { Opcode = Op; }
159 unsigned getOpcode() const { return Opcode; }
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| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 171 unsigned Opcode = BinOp->getOpcode();
218 else if (NextLevelBinOp->getOpcode() != Opcode)
240 unsigned &Opcode, Type *&Ty) {
282 Opcode = RdxStart->getOpcode();
303 unsigned &Opcode, Type *&Ty) {
373 Opcode = RdxOpcode;
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| /external/llvm/lib/DebugInfo/DWARF/ |
| DWARFDebugFrame.cpp | 64 /// opcode and an optional sequence of operands.
67 Instruction(uint8_t Opcode)
68 : Opcode(Opcode)
71 uint8_t Opcode;
77 /// Convenience methods to add a new instruction with the given opcode and
79 void addInstruction(uint8_t Opcode) {
80 Instructions.push_back(Instruction(Opcode));
83 void addInstruction(uint8_t Opcode, uint64_t Operand1) {
84 Instructions.push_back(Instruction(Opcode));
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 195 const char *Instruction::getOpcodeName(unsigned OpCode) {
196 switch (OpCode) {
350 // We have two instructions of identical opcode and #operands. Check to see
379 // We have two instructions of identical opcode and #operands. Check to see
493 bool Instruction::isAssociative(unsigned Opcode) {
494 return Opcode == And || Opcode == Or || Opcode == Xor ||
495 Opcode == Add || Opcode == Mul
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.cpp | 297 int Opcode = SU->getInstr()->getOpcode();
299 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
302 if (TII->isALUInstr(Opcode)) {
306 switch (Opcode) {
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 191 unsigned Opcode = MCID.getOpcode();
192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
199 static bool isFpMulInstruction(unsigned Opcode) {
200 switch (Opcode) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 334 unsigned Opcode = 0;
337 Opcode = MSP430::MOV8rm_POST;
340 Opcode = MSP430::MOV16rm_POST;
346 return CurDAG->getMachineNode(Opcode, SDLoc(N),
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 55 unsigned Opcode = Mips::Mflo16;
56 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
60 unsigned Opcode = Mips::Mfhi16;
61 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
246 unsigned Opcode = Node->getOpcode();
256 switch(Opcode) {
268 if (Opcode == ISD::ADDE) {
297 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
311 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 248 unsigned Opcode;
301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
302 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
303 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
304 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
305 case Intrinsic::rint: Opcode = ISD::FRINT; break;
306 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
307 case Intrinsic::round: Opcode = ISD::FROUND; break;
342 Opcode = ISD::FSQRT; break;
346 Opcode = ISD::FFLOOR; break
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
363 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
371 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
373 CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MulLHS, MulRHS);
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| SparcInstrInfo.cpp | 177 unsigned Opcode = I->getOpcode();
178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
179 return true; // Unknown Opcode.
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 178 unsigned Opcode = MI->getOpcode();
180 if (Opcode == SystemZ::AHI)
182 else if (Opcode == SystemZ::AGHI)
224 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
225 if (!Opcode)
228 MI->setDesc(TII->get(Opcode));
242 int Opcode = MI->getOpcode();
243 const MCInstrDesc &Desc = TII->get(Opcode);
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| SystemZFrameLowering.cpp | 292 unsigned Opcode;
295 Opcode = SystemZ::AGHI;
297 Opcode = SystemZ::AGFI;
306 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
431 unsigned Opcode = MBBI->getOpcode();
432 if (Opcode != SystemZ::LMG)
438 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
447 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
|
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 262 int Opcode = MI->getOpcode();
263 if (Opcode == X86::MOV32mi || Opcode == X86::MOV32mr)
|
| X86FixupLEAs.cpp | 236 static inline bool isLEA(const int opcode) {
237 return opcode == X86::LEA16r || opcode == X86::LEA32r ||
238 opcode == X86::LEA64r || opcode == X86::LEA64_32r;
259 int Opcode = MI->getOpcode();
260 if (!isLEA(Opcode))
266 switch (Opcode) {
294 int opcode = MI->getOpcode(); local
296 int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags, opcode);
332 const int opcode = MI->getOpcode(); local
[all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 278 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
279 switch (Opcode) {
441 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
443 switch (Opcode) {
670 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
671 switch (Opcode) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 65 int Opcode = MI->getOpcode();
66 if (Opcode == XCore::LDWFI)
87 int Opcode = MI->getOpcode();
88 if (Opcode == XCore::STWFI)
136 /// the correspondent Branch instruction opcode.
149 /// opcode that matches the cc.
403 /// ReverseBranchCondition - Return the inverse opcode of the
443 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
444 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 232 unsigned Opcode = J->getOpcode();
233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
234 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
235 bool UseSignedOp = Opcode == Instruction::SDiv ||
236 Opcode == Instruction::SRem;
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| rc_test_helpers.c | 297 struct match_info Opcode;
334 tokens.Opcode.String = inst_str + matches[1].rm_so;
335 tokens.Opcode.Length = match_length(matches, 1);
347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) {
350 inst->U.I.Opcode = info->Opcode;
|
| /external/v8/src/compiler/ |
| operator.h | 33 typedef uint16_t Opcode;
55 Operator(Opcode opcode, Properties properties, const char* mnemonic,
63 // the opcode is stored directly in the operator object.
64 Opcode opcode() const { return opcode_; } function in class:v8::internal::compiler::Operator
74 return this->opcode() == that->opcode();
80 virtual size_t HashCode() const { return base::hash<Opcode>()(opcode()); }
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| evntprov.h | 61 UCHAR Opcode;
194 UCHAR Opcode,
202 EventDescriptor->Opcode = Opcode;
243 return (EventDescriptor->Opcode);
304 UCHAR Opcode)
306 EventDescriptor->Opcode = Opcode;
|
| /art/runtime/quick/ |
| inline_method_analyser.cc | 60 template <Instruction::Code opcode> bool Opcode();
112 template <Instruction::Code opcode>
113 bool Matcher::Opcode() {
114 return instruction_->Opcode() == opcode;
119 return IsInstructionDirectConst(instruction_->Opcode()) &&
120 (instruction_->Opcode() == Instruction::CONST_WIDE ? instruction_->VRegB_51l() == 0
126 return IsInstructionIPut(instruction_->Opcode()) &&
144 DCHECK_EQ(invoke_direct->Opcode(), Instruction::INVOKE_DIRECT)
468 Instruction::Code opcode = instruction->Opcode(); local
599 Instruction::Code opcode = instruction->Opcode(); local
664 Instruction::Code opcode = instruction->Opcode(); local
[all...] |
