| /external/llvm/test/CodeGen/X86/ |
| fold-tied-op.ll | 9 ; CHECK: shldl {{.*#+}} 4-byte Folded Spill
11 ; CHECK: shldl {{.*#+}} 4-byte Folded Spill
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| musttail-fastcall.ll | 22 ; Check that we spill and fill around the call to puts.
51 ; Check that we spill and fill SSE registers around the call to puts.
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| win-catchpad-varargs.ll | 38 ; X64: movl $-1, -20(%rbp) # 4-byte Folded Spill
60 ; X64: movl %eax, -20(%rbp) # 4-byte Spill
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| win64_eh.ll | 162 ; WIN64: movaps %xmm7, -16(%rbp) # 16-byte Spill
164 ; WIN64: movaps %xmm6, -32(%rbp) # 16-byte Spill
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| /external/v8/src/compiler/ |
| live-range-separator.cc | 40 // Ensure the original range has a spill range associated, before it gets
42 // reuse spill slots of splinters, during allocation, we avoid clobbering
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| register-allocator.h | 334 void Spill();
533 // Spill range management.
655 // just for spill in a single deferred block.
[all...] |
| /external/v8/test/mjsunit/ |
| codegen-coverage.js | 53 // The call will spill registers and leave x in {eax,rax}.
55 // The add will spill x and reuse {eax,rax} for the result.
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| opc-m.pl | 35 foreach $s ("1", "2", "4", "8", "1.rel", "2.rel", "4.rel", "8.rel", "8.spill") {
70 foreach $s ( "fs", "fd", "f8", "fe", "f.spill" ) {
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| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 33 /// spill locations) can be stored.
114 /// assignCalleeSavedSpillSlots - Allows target to override spill slot
117 /// returns false, spill slots will be assigned using generic implementation.
134 /// allowed to spill it anywhere it chooses.
181 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
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| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 256 /// the spill instruction refers to an undefined register. This code needs
768 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
775 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
782 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
789 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
[all...] |
| /external/v8/src/crankshaft/x87/ |
| lithium-gap-resolver-x87.cc | 240 // 3. Prefer to spill a register that is not used in any remaining move
283 // Spill on demand to use a temporary register for memory-to-memory
382 // spill on demand because the simple spill implementation cannot avoid
400 // Memory-memory. Spill on demand to use a temporary. If there is a
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| /art/compiler/utils/x86_64/ |
| assembler_x86_64.cc | 2649 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2667 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2680 ManagedRegisterSpill spill = entry_spills.at(i); local
2708 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
2721 x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); local
[all...] |
| /external/v8/src/crankshaft/ |
| lithium-allocator.cc | 189 // We cannot spill a live range that has a use requiring a register
793 // This value is produced on the stack, we never need to spill it.
805 // This move to spill operand is not a real use. Liveness analysis
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFrameInfo.h | 71 /// example, register allocator spill code never needs variable sized
100 // If true the stack object is used as spill slot. It
113 // Normally, spill slots and fixed-offset objects don't alias IR-accessible
515 /// Create a spill slot at a fixed location on the stack.
543 /// Returns true if the specified index corresponds to a spill slot.
570 /// Create a new statically sized stack object that represents a spill slot,
612 /// Before the PrologueEpilogueInserter has placed the CSR spill code, this
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| /external/llvm/lib/CodeGen/ |
| RegAllocPBQP.cpp | 14 // register assignment. If any variables are selected for spilling then spill
132 /// \brief Spill the given VReg.
153 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
159 // A minimum spill costs, so that register constraints can can be set
635 VRegSpiller.spill(LRE);
647 assert(!LI.empty() && "Empty spill range.");
683 // Spill VReg. If this introduces new intervals we'll need another round
718 // All intervals have a spill weight that is mostly proportional to the number
744 // * Spill if necessary
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| RegAllocFast.cpp | 75 bool Dirty; // Register needs spill.
207 // Allocate a new stack object for this spill location...
282 // instruction, not on the spill.
315 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
327 /// spillAll - Spill all dirty virtregs without killing them.
532 // Ignore the hint if we would have to spill a dirty register.
721 // we must spill and reallocate.
868 // Modify DBG_VALUE now that the value is in a spill slot
[all...] |
| RegAllocGreedy.cpp | 59 SplitSpillMode("split-spill-mode", cl::Hidden,
60 cl::desc("Spill mode for splitting live ranges"),
232 float MaxWeight; ///< Maximum spill weight evicted.
754 // Never evict spill products. They cannot split or spill.
758 // register for it. This is indicated by an infinite spill weight. These
869 // hints, and only evict smaller spill weights
[all...] |
| LiveStackAnalysis.cpp | 61 assert(Slot >= 0 && "Spill slot indice must be >= 0");
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 127 // We spill the argument registers on ARM to free them up for scratch use, we then assume
240 // Compute spill mask to agree with callee saves initialized in the constructor
263 // Plus return value spill area size
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| /external/llvm/test/CodeGen/SystemZ/ |
| frame-17.ll | 6 ; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly
71 ; Same for doubles, except that the full spill slot is used.
132 ; The long double case needs a 16-byte spill slot.
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| /art/compiler/utils/x86/ |
| assembler_x86.cc | 1935 Register spill = spill_regs.at(i).AsX86().AsCpuRegister(); local
1953 ManagedRegisterSpill spill = entry_spills.at(i); local
1977 Register spill = spill_regs.at(i).AsX86().AsCpuRegister(); local
[all...] |
| /art/runtime/arch/mips64/ |
| quick_method_frame_info_mips64.h | 44 // F12 should not be necessary to spill, as A0 is always in use.
|
| /art/runtime/arch/x86_64/ |
| context_x86_64.cc | 44 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
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| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 221 // to the stack pointer, so only put the emergency spill slot next to the
281 // Assume that we'll have at least some spill slots allocated.
284 Offset += 128; // 128 bytes of spill slots
388 "Emergency spill slot is out of reach");
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| AArch64RegisterInfo.h | 45 // value of 1 << 14. A value of 5 will choose to spill or split really
|
