| /external/valgrind/VEX/priv/ |
| host_generic_regs.h | 97 needed to spill each class of register. It allocates the following
466 /* Return insn(s) to spill/restore a real reg to a spill slot
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ia64-opc-m.c | [all...] |
| /packages/apps/Messaging/res/values-nb/ |
| strings.xml | 40 <string name="mediapicker_cameraChooserDescription" msgid="8498255650058981250">"Ta bilder eller spill inn video"</string>
42 <string name="mediapicker_audioChooserDescription" msgid="3660616501040372452">"Spill inn lyd"</string>
49 <string name="mediapicker_audio_title" msgid="5455016591560739789">"Spill inn lyd"</string>
203 <string name="audio_play_content_description" msgid="4932509227281251607">"Spill av lydvedlegg"</string>
317 <string name="video_thumbnail_view_play_button_content_description" msgid="3506938388391260811">"Spill av videoen"</string>
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 836 ; Spill general-purpose registers
860 .seh_stackalloc (size of XMM spill slots)
861 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
865 ; Spill XMMs
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDKernelCodeT.h | 327 /// Scratch Wave Offset as an offset, to access the Private/Spill/Arg
449 /// dispatch scratch base. Must be used as an offset with Private/Spill/Arg
554 /// The amount of memory required for the combined private, spill
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| README.txt | 369 This is functional, but there is no reason to spill the LR register all the way
384 reg, it would ask "what is the best class to copy this into that I *can* spill"
386 register of that class. If it is then later necessary to spill that reg, so be
|
| /external/llvm/test/CodeGen/AArch64/ |
| aarch64-dynamic-stack-layout.ll | 347 ; spill slots
408 ; spill slots
459 ; spill slots
|
| /external/llvm/test/CodeGen/ARM/ |
| arm-shrink-wrapping.ll | 13 ; Otherwise, we may have spill right in the entry block, defeating
631 ; This function needs to spill floating point registers to
633 ; to access debug info location while inserting the spill code
|
| /art/runtime/interpreter/mterp/x86_64/ |
| header.S | 141 /* Spill offsets relative to %esp */
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonTargetMachine.cpp | 283 // Expand Spill code for predicate registers.
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 199 // Add the callee-saved register as live-in. It's killed at the spill.
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPrologEpilogPass.cpp | 185 // Then assign frame offsets to stack objects that are not used to spill
|
| NVPTXTargetMachine.cpp | 294 // which merges spill slots.
|
| /external/llvm/test/CodeGen/Mips/ |
| fp64a.ll | 1 ; Test that the FP64A ABI performs double precision moves via a spill/reload.
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| spill.ll | 1 ; Test that the correct instruction is chosen for spill and reload by trying
150 ; CHECK: st.b {{.*}} Spill
151 ; CHECK: st.b {{.*}} Spill
299 ; CHECK: st.h {{.*}} Spill
300 ; CHECK: st.h {{.*}} Spill
448 ; CHECK: st.w {{.*}} Spill
449 ; CHECK: st.w {{.*}} Spill
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| ppc-shrink-wrapping.ll | 6 ; Otherwise, we may have spill right in the entry block, defeating
378 ; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
380 ; DISABLE: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
632 ; CHECK: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
|
| /external/llvm/test/CodeGen/SystemZ/ |
| bswap-02.ll | 101 ; Test a case where we spill the source of at least one LRVR. We want
|
| bswap-03.ll | 101 ; Test a case where we spill the source of at least one LRVGR. We want
|
| frame-04.ll | 6 ; This function should require all FPRs, but no other spill slots.
|
| frame-05.ll | 5 ; This function should require all GPRs, but no other spill slots. The caller
|
| frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
|
| int-conv-01.ll | 107 ; Test a case where we spill the source of at least one LBR. We want
|
| int-conv-02.ll | 117 ; Test a case where we spill the source of at least one LLCR. We want
|
| int-conv-03.ll | 107 ; Test a case where we spill the source of at least one LGBR. We want
|
