| /external/llvm/test/CodeGen/AMDGPU/ |
| drop-mem-operand-move-smrd.ll | 4 ; when replaced with the addr64 during operand legalization, resulting
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| mad-sub.ll | 173 ; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
174 ; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
194 ; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
195 ; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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| llvm.AMDGPU.div_fmas.ll | 108 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
109 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
110 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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| madak.ll | 33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
34 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
35 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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| mubuf.ll | 46 ; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0
128 ; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0
171 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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| ds_write2.ll | 25 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
26 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
144 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
145 ; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
304 ; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
305 ; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
|
| /external/clang/test/CodeGen/ |
| c11atomics.c | 376 // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
378 // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
402 // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
407 // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
427 // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
433 // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
461 // CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
470 // CHECK: [[ADDR8:%.*]] = bitcast i64* [[ADDR64]] to i8*
|
| /external/valgrind/VEX/useful/ |
| smchash.c | 8 typedef unsigned long long int Addr64;
23 Addr64 ga;
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| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 100 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
[all...] |
| SIInstrFormats.td | 462 bits<1> addr64;
475 let Inst{15} = addr64;
493 bits<1> addr64;
506 let Inst{15} = addr64;
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| SIInstrInfo.td | 483 def addr64 : Operand<i1> {
[all...] |
| SIInstrInfo.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.h | 604 to it. May be conditional. Urr, use of Addr64 implicitly
607 Addr64 dstGA; /* next guest address */
638 Addr64 target;
895 extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC,
903 extern ARM64Instr* ARM64Instr_Call ( ARM64CondCode, Addr64, Int nArgRegs,
[all...] |
| host_mips_defs.h | 449 Addr64 target;
458 Addr64 dstGA; /* next guest address */
635 extern MIPSInstr *MIPSInstr_Call ( MIPSCondCode, Addr64, UInt, HReg, RetLoc );
636 extern MIPSInstr *MIPSInstr_CallAlways ( MIPSCondCode, Addr64, UInt, RetLoc );
638 extern MIPSInstr *MIPSInstr_XDirect ( Addr64 dstGA, MIPSAMode* amPC,
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| host_tilegx_defs.h | 405 Addr64 target;
415 Addr64 dstGA; /* next guest address */
501 extern TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode, Addr64, ULong, HReg );
502 extern TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode, Addr64, ULong );
503 extern TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC,
|
| host_amd64_defs.h | 476 Addr64 target;
483 Addr64 dstGA; /* next guest address */
733 extern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int, RetLoc );
734 extern AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP,
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| host_s390_defs.h | 372 Addr64 target;
593 Addr64 dst; /* next guest address */
653 s390_insn *s390_insn_helper_call(s390_cc_t cond, Addr64 target, UInt num_args,
723 s390_insn *s390_insn_xdirect(s390_cc_t cond, Addr64 dst, s390_amode *guest_IA,
|
| host_ppc_defs.h | 615 Addr64 target;
620 to it. May be conditional. Use of Addr64 in order to cope
623 Addr64 dstGA; /* next guest address */
1009 extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc );
1010 extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
[all...] |
| host_tilegx_isel.c | 112 Addr64 max_ga;
[all...] |
| guest_tilegx_toIR.c | 63 static Addr64 guest_PC_bbstart;
67 static Addr64 guest_PC_curr_instr;
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 118 defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>;
120 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
|
| /external/valgrind/coregrind/m_gdbserver/ |
| valgrind-low-s390x.c | 203 return (CORE_ADDR**)((Addr)((Addr64)s390x->guest_a0 << 32
204 | (Addr64)s390x->guest_a1)
|
| /external/valgrind/coregrind/ |
| pub_core_gdbserver.h | 214 Addr64 invoke_gdbserver;
216 Addr64 threads;
|
| /external/elfutils/backends/ |
| ppc64_reloc.def | 66 RELOC_TYPE (ADDR64, REL|EXEC|DYN)
|
| /external/valgrind/VEX/pub/ |
| libvex_basictypes.h | 133 typedef ULong Addr64;
|
