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  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-m68hc11/
relax-direct.s 1 ;;; Test 68HC11 linker relaxation from extended addressing to direct
2 ;;; addressing modes
66 ;; 'tst' does not support direct addressing mode.
  /external/llvm/test/CodeGen/Hexagon/
absimm.ll 2 ; Check that we generate absolute addressing mode instructions
pred-absolute-store.ll 3 ; addressing mode.
  /external/v8/src/compiler/mips/
instruction-codes-mips.h 107 // Addressing modes represent the "shape" of inputs to an instruction.
108 // Many instructions support multiple addressing modes. Addressing modes
112 // We use the following local notation for addressing modes:
  /external/v8/src/compiler/mips64/
instruction-codes-mips64.h 134 // Addressing modes represent the "shape" of inputs to an instruction.
135 // Many instructions support multiple addressing modes. Addressing modes
139 // We use the following local notation for addressing modes:
  /external/v8/src/compiler/ppc/
instruction-codes-ppc.h 118 // Addressing modes represent the "shape" of inputs to an instruction.
119 // Many instructions support multiple addressing modes. Addressing modes
123 // We use the following local notation for addressing modes:
  /external/v8/src/compiler/x87/
instruction-codes-x87.h 88 // Addressing modes represent the "shape" of inputs to an instruction.
89 // Many instructions support multiple addressing modes. Addressing modes
93 // We use the following local notation for addressing modes:
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/
tic4x.exp 65 # Test all addressing modes
69 # Make sure the c4x addressing dont work on c3x
70 gas_test_error "addressing.s" "-m30 --defsym TEST_C4X=1" "c4x addressing usage in c3x"
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
address.s 1 ;; test all addressing permutations
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
t16-bad.l 122 [^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!'
123 [^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4'
124 [^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]'
125 [^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2'
129 [^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!'
130 [^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4'
131 [^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]'
132 [^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2'
136 [^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!'
137 [^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4
    [all...]
  /external/libusb-compat/
NEWS 12 * Further improvements to match libusb-0.1 endpoint addressing behaviour
21 * Match libusb-0.1 endpoint addressing behaviour
  /external/llvm/test/Analysis/CostModel/
no_info.ll 18 %p = getelementptr i8, i8* %a, i32 %b ; NoTTI accepts reg+reg addressing.
26 ; NoTTI rejects reg+scale*reg addressing.
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
x86_64.s 3 # REX prefix and addressing modes.
113 #addressing modes:
115 #absolute 64bit addressing
118 #absolute 32bit addressing
139 #addressing modes
141 #absolute 64bit addressing
144 #absolute 32bit addressing
155 #absolute 64bit addressing
173 #absolute signed 32bit addressing
  /external/v8/src/compiler/arm/
instruction-codes-arm.h 104 // Addressing modes represent the "shape" of inputs to an instruction.
105 // Many instructions support multiple addressing modes. Addressing modes
  /frameworks/av/media/libstagefright/codecs/amrnb/enc/
Android.mk 74 #addressing b/25409744
98 #addressing b/25409744
131 #addressing b/25409744
  /external/chromium-trace/catapult/third_party/gsutil/third_party/pyasn1/
TODO 3 addressing
  /external/llvm/test/CodeGen/ARM/
lsr-scale-addr-mode.ll 2 ; Should use scaled addressing mode.
  /external/llvm/test/CodeGen/X86/
fast-isel-constpool.ll 4 ; Make sure fast isel uses rip-relative addressing for the small code model.
rip-rel-address.ll 4 ; Use %rip-relative addressing even in static mode on x86-64, because
rip-rel-lea.ll 5 ; Use %rip-relative addressing even in static mode on x86-64, because
  /external/llvm/test/Transforms/LoopStrengthReduce/
dont_reduce_bytes.ll 2 ; support an efficient 'mem[r1+r2]' addressing mode.
  /external/v8/src/compiler/arm64/
instruction-codes-arm64.h 147 // Addressing modes represent the "shape" of inputs to an instruction.
148 // Many instructions support multiple addressing modes. Addressing modes
152 // We use the following local notation for addressing modes:
  /external/v8/src/compiler/ia32/
instruction-codes-ia32.h 105 // Addressing modes represent the "shape" of inputs to an instruction.
106 // Many instructions support multiple addressing modes. Addressing modes
110 // We use the following local notation for addressing modes:
  /external/v8/src/compiler/
instruction-codes.h 92 // Addressing modes represent the "shape" of inputs to an instruction.
93 // Many instructions support multiple addressing modes. Addressing modes
157 // for code generation. We encode the instruction, addressing mode, and flags
  /external/v8/src/compiler/x64/
instruction-codes-x64.h 139 // Addressing modes represent the "shape" of inputs to an instruction.
140 // Many instructions support multiple addressing modes. Addressing modes
144 // We use the following local notation for addressing modes:

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