1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(Mips64Add) \ 16 V(Mips64Dadd) \ 17 V(Mips64DaddOvf) \ 18 V(Mips64Sub) \ 19 V(Mips64Dsub) \ 20 V(Mips64DsubOvf) \ 21 V(Mips64Mul) \ 22 V(Mips64MulHigh) \ 23 V(Mips64DMulHigh) \ 24 V(Mips64MulHighU) \ 25 V(Mips64Dmul) \ 26 V(Mips64Div) \ 27 V(Mips64Ddiv) \ 28 V(Mips64DivU) \ 29 V(Mips64DdivU) \ 30 V(Mips64Mod) \ 31 V(Mips64Dmod) \ 32 V(Mips64ModU) \ 33 V(Mips64DmodU) \ 34 V(Mips64And) \ 35 V(Mips64Or) \ 36 V(Mips64Nor) \ 37 V(Mips64Xor) \ 38 V(Mips64Clz) \ 39 V(Mips64Shl) \ 40 V(Mips64Shr) \ 41 V(Mips64Sar) \ 42 V(Mips64Ext) \ 43 V(Mips64Ins) \ 44 V(Mips64Dext) \ 45 V(Mips64Dins) \ 46 V(Mips64Dclz) \ 47 V(Mips64Dshl) \ 48 V(Mips64Dshr) \ 49 V(Mips64Dsar) \ 50 V(Mips64Ror) \ 51 V(Mips64Dror) \ 52 V(Mips64Mov) \ 53 V(Mips64Tst) \ 54 V(Mips64Cmp) \ 55 V(Mips64CmpS) \ 56 V(Mips64AddS) \ 57 V(Mips64SubS) \ 58 V(Mips64MulS) \ 59 V(Mips64DivS) \ 60 V(Mips64ModS) \ 61 V(Mips64AbsS) \ 62 V(Mips64SqrtS) \ 63 V(Mips64MaxS) \ 64 V(Mips64MinS) \ 65 V(Mips64CmpD) \ 66 V(Mips64AddD) \ 67 V(Mips64SubD) \ 68 V(Mips64MulD) \ 69 V(Mips64DivD) \ 70 V(Mips64ModD) \ 71 V(Mips64AbsD) \ 72 V(Mips64SqrtD) \ 73 V(Mips64MaxD) \ 74 V(Mips64MinD) \ 75 V(Mips64Float64RoundDown) \ 76 V(Mips64Float64RoundTruncate) \ 77 V(Mips64Float64RoundUp) \ 78 V(Mips64Float64RoundTiesEven) \ 79 V(Mips64Float32RoundDown) \ 80 V(Mips64Float32RoundTruncate) \ 81 V(Mips64Float32RoundUp) \ 82 V(Mips64Float32RoundTiesEven) \ 83 V(Mips64CvtSD) \ 84 V(Mips64CvtDS) \ 85 V(Mips64TruncWD) \ 86 V(Mips64RoundWD) \ 87 V(Mips64FloorWD) \ 88 V(Mips64CeilWD) \ 89 V(Mips64TruncWS) \ 90 V(Mips64RoundWS) \ 91 V(Mips64FloorWS) \ 92 V(Mips64CeilWS) \ 93 V(Mips64TruncLS) \ 94 V(Mips64TruncLD) \ 95 V(Mips64TruncUwD) \ 96 V(Mips64TruncUlS) \ 97 V(Mips64TruncUlD) \ 98 V(Mips64CvtDW) \ 99 V(Mips64CvtSL) \ 100 V(Mips64CvtSW) \ 101 V(Mips64CvtSUl) \ 102 V(Mips64CvtDL) \ 103 V(Mips64CvtDUw) \ 104 V(Mips64CvtDUl) \ 105 V(Mips64Lb) \ 106 V(Mips64Lbu) \ 107 V(Mips64Sb) \ 108 V(Mips64Lh) \ 109 V(Mips64Lhu) \ 110 V(Mips64Sh) \ 111 V(Mips64Ld) \ 112 V(Mips64Lw) \ 113 V(Mips64Sw) \ 114 V(Mips64Sd) \ 115 V(Mips64Lwc1) \ 116 V(Mips64Swc1) \ 117 V(Mips64Ldc1) \ 118 V(Mips64Sdc1) \ 119 V(Mips64BitcastDL) \ 120 V(Mips64BitcastLD) \ 121 V(Mips64Float64ExtractLowWord32) \ 122 V(Mips64Float64ExtractHighWord32) \ 123 V(Mips64Float64InsertLowWord32) \ 124 V(Mips64Float64InsertHighWord32) \ 125 V(Mips64Float64Max) \ 126 V(Mips64Float64Min) \ 127 V(Mips64Float32Max) \ 128 V(Mips64Float32Min) \ 129 V(Mips64Push) \ 130 V(Mips64StoreToStackSlot) \ 131 V(Mips64StackClaim) 132 133 134 // Addressing modes represent the "shape" of inputs to an instruction. 135 // Many instructions support multiple addressing modes. Addressing modes 136 // are encoded into the InstructionCode of the instruction and tell the 137 // code generator after register allocation which assembler method to call. 138 // 139 // We use the following local notation for addressing modes: 140 // 141 // R = register 142 // O = register or stack slot 143 // D = double register 144 // I = immediate (handle, external, int32) 145 // MRI = [register + immediate] 146 // MRR = [register + register] 147 // TODO(plind): Add the new r6 address modes. 148 #define TARGET_ADDRESSING_MODE_LIST(V) \ 149 V(MRI) /* [%r0 + K] */ \ 150 V(MRR) /* [%r0 + %r1] */ 151 152 153 } // namespace compiler 154 } // namespace internal 155 } // namespace v8 156 157 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 158
