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  /external/v8/src/full-codegen/mips/
full-codegen-mips.cc 36 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
59 __ andi(at, reg, 0);
70 __ andi(at, reg, 0);
79 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
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  /external/v8/src/full-codegen/mips64/
full-codegen-mips64.cc 36 // marker is a andi zero_reg, rx, #yyyy instruction, and rx * 0x0000ffff + yyyy
59 __ andi(at, reg, 0);
70 __ andi(at, reg, 0);
79 __ andi(zero_reg, reg, delta_to_patch_site % kImm16Mask);
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  /external/v8/src/regexp/ppc/
regexp-macro-assembler-ppc.cc 499 __ andi(r4, current_character(), Operand(kTableSize - 1));
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  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
loopfilter_filters_altivec.asm 831 andi. r7, r3, 8 ;# row origin modulo 16
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  /system/core/libpixelflinger/codeflinger/
MIPS64Assembler.cpp 420 mMips->ANDI(Rd, Rn, src);
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  /toolchain/binutils/binutils-2.25/bfd/
elf32-sh-relocs.h 624 /* Used in ADDI, ANDI et al. */
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  /toolchain/binutils/binutils-2.25/cpu/
or1korbis.cpu 161 ("ANDI" #x29)
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sh64-media.cpu 239 (dshmi andi "AND immediate"
241 "andi $rm, $disp10, $rd"
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  /toolchain/binutils/binutils-2.25/include/opcode/
spu-insns.h 217 APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
  /toolchain/binutils/binutils-2.25/opcodes/
m68k-opc.c 82 {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up },
83 {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up },
84 {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up },
86 /* The and opcode can generate the andi instruction. */
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iq2000-opc.c 311 /* andi ${rt-rs},$lo16 */
317 /* andi $rt,$rs,$lo16 */
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micromips-opc.c 346 {"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
347 {"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
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  /external/valgrind/VEX/switchback/
test_ppc_jm1.c 1208 __asm__ __volatile__ ("andi. 17, 14, 0");
1217 { &test_andi_ , " andi.", },
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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
micromips@msa.d 468 [0-9a-f]+ <[^>]*> 5800 5241 andi\.b \$w9,\$w10,0x0
469 [0-9a-f]+ <[^>]*> 58ff 62c1 andi\.b \$w11,\$w12,0xff
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mipsr6@msa.d 468 [0-9a-f]+ <[^>]*> 78005240 andi\.b \$w9,\$w10,0x0
469 [0-9a-f]+ <[^>]*> 78ff62c0 andi\.b \$w11,\$w12,0xff
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msa.d 467 [0-9a-f]+ <[^>]*> 78005240 andi\.b \$w9,\$w10,0x0
468 [0-9a-f]+ <[^>]*> 78ff62c0 andi\.b \$w11,\$w12,0xff
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  /external/valgrind/VEX/priv/
host_ppc_isel.c 659 andi %tmp, nElems-1
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guest_tilegx_toIR.c 582 case 30: /* "andi" */
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  /art/runtime/interpreter/mterp/out/
mterp_mips.S 264 #define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255
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  /toolchain/binutils/binutils-2.25/gas/config/
tc-score7.c 674 {"andi", 0x02080000, 0x3e0e0001, 0x8000, Rd_I16, s7_do_rdi16},
675 {"andi.c", 0x02080001, 0x3e0e0001, 0x8000, Rd_I16, s7_do_rdi16},
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  /external/llvm/lib/Target/PowerPC/
PPCInstr64Bit.td 440 "andi. $dst, $src1, $src2", IIC_IntGeneral,
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  /external/v8/src/mips/
assembler-mips.h 735 void andi(Register rd, Register rs, int32_t j);
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  /external/v8/src/mips64/
assembler-mips64.h 758 void andi(Register rd, Register rs, int32_t j);
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  /frameworks/base/packages/SystemUI/res/values-is-rIS/
strings.xml     [all...]
  /toolchain/binutils/binutils-2.25/binutils/
ChangeLog-2007 549 2007-06-18 Andi Kleen <ak@suse.de>
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