| /external/v8/test/cctest/ |
| test-disasm-mips64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6-n32.d | 458 0+0524 <[^>]*> f8400000 bnezc v0,00000528 <[^>]*>
461 0+052c <[^>]*> f8400000 bnezc v0,00000530 <[^>]*>
464 0+0534 <[^>]*> f8400000 bnezc v0,00000538 <[^>]*>
467 0+053c <[^>]*> f8400000 bnezc v0,00000540 <[^>]*>
|
| r6.d | 457 0+0524 <[^>]*> f85fffff bnezc v0,00000524 <[^>]*>
460 0+052c <[^>]*> f8500000 bnezc v0,ffc00530 <[^>]*>
463 0+0534 <[^>]*> f84fffff bnezc v0,00400534 <[^>]*>
466 0+053c <[^>]*> f85fffff bnezc v0,0000053c <[^>]*>
|
| r6-n64.d | 694 0+0524 <[^>]*> f8400000 bnezc v0,0+0528 <[^>]*>
699 0+052c <[^>]*> f8400000 bnezc v0,0+0530 <[^>]*>
704 0+0534 <[^>]*> f8400000 bnezc v0,0+0538 <[^>]*>
709 0+053c <[^>]*> f8400000 bnezc v0,0+0540 <[^>]*>
|
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips64.S | 874 bnezc v0, MterpException
897 bnezc v0, MterpException
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 241 void Bnezc(Register rs, uint32_t imm21); // R6
640 // is an exception: use kOffset23 for beqzc/bnezc).
691 // Branch instructions have signed offsets of 16, 19 (addiupc), 21 (beqzc/bnezc),
[all...] |
| assembler_mips.cc | 710 void MipsAssembler::Bnezc(Register rs, uint32_t imm21) {
822 Bnezc(rs, imm16_21);
[all...] |
| /external/v8/src/ic/mips/ |
| ic-mips.cc | [all...] |
| /external/v8/src/ic/mips64/ |
| ic-mips64.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSchedule.td | 43 def II_BCCZC : InstrItinClass; // beqzc, bnezc
|
| Mips32r6InstrInfo.td | 356 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
686 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
[all...] |
| MipsDelaySlotFiller.cpp | 613 // branch instruction, i.e. BEQZC or BNEZC.
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 28 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256
|
| valid-mips32r6.txt | 174 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| valid.s | 48 bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 58 bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90]
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 621 void Mips64Assembler::Bnezc(GpuRegister rs, uint32_t imm21) {
679 Bnezc(rs, imm16_21);
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 680 void bnezc(Register rt, int32_t offset);
681 inline void bnezc(Register rt, Label* L) {
682 bnezc(rt, shifted_branch_offset21(L));
[all...] |
| assembler-mips.cc | 479 (opcode == POP76 && rs_field != 0); // BNEZC
494 // Checks if the instruction is BEQZC or BNEZC.
928 // Checks BEQZC or BNEZC.
1450 void Assembler::bnezc(Register rs, int32_t offset) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 684 void bnezc(Register rt, int32_t offset);
685 inline void bnezc(Register rt, Label* L) {
686 bnezc(rt, shifted_branch_offset21(L));
[all...] |
| assembler-mips64.cc | 453 (opcode == POP76 && rs_field != 0); // BNEZC
468 // Checks if the instruction is BEQZC or BNEZC.
945 // Checks BEQZC or BNEZC.
1480 void Assembler::bnezc(Register rs, int32_t offset) { function in class:v8::internal::Assembler
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| valid-el.txt | 161 0xa9 0x40 0x9a 0x02 # CHECK: bnezc $9, 1332
|
| valid.txt | 161 0x40 0xa9 0x02 0x9a # CHECK: bnezc $9, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 38 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256
|
| valid-mips64r6.txt | 199 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256
|
