1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips32r6 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 include "Mips32r6InstrFormats.td" 15 16 // Notes about removals/changes from MIPS32r6: 17 // Reencoded: jr -> jalr 18 // Reencoded: jr.hb -> jalr.hb 19 20 def brtarget21 : Operand<OtherVT> { 21 let EncoderMethod = "getBranchTarget21OpValue"; 22 let OperandType = "OPERAND_PCREL"; 23 let DecoderMethod = "DecodeBranchTarget21"; 24 let ParserMatchClass = MipsJumpTargetAsmOperand; 25 } 26 27 def brtarget26 : Operand<OtherVT> { 28 let EncoderMethod = "getBranchTarget26OpValue"; 29 let OperandType = "OPERAND_PCREL"; 30 let DecoderMethod = "DecodeBranchTarget26"; 31 let ParserMatchClass = MipsJumpTargetAsmOperand; 32 } 33 34 def jmpoffset16 : Operand<OtherVT> { 35 let EncoderMethod = "getJumpOffset16OpValue"; 36 let ParserMatchClass = MipsJumpTargetAsmOperand; 37 } 38 39 def calloffset16 : Operand<iPTR> { 40 let EncoderMethod = "getJumpOffset16OpValue"; 41 let ParserMatchClass = MipsJumpTargetAsmOperand; 42 } 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Instruction Encodings 47 // 48 //===----------------------------------------------------------------------===// 49 50 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; 51 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; 52 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; 53 class AUI_ENC : AUI_FM; 54 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; 55 56 class BAL_ENC : BAL_FM; 57 class BALC_ENC : BRANCH_OFF26_FM<0b111010>; 58 class BC_ENC : BRANCH_OFF26_FM<0b110010>; 59 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 60 DecodeDisambiguates<"AddiGroupBranch">; 61 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>, 62 DecodeDisambiguatedBy<"DaddiGroupBranch">; 63 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 64 DecodeDisambiguates<"DaddiGroupBranch">; 65 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>, 66 DecodeDisambiguatedBy<"DaddiGroupBranch">; 67 68 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>, 69 DecodeDisambiguates<"BgtzlGroupBranch">; 70 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>, 71 DecodeDisambiguatedBy<"BlezlGroupBranch">; 72 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>, 73 DecodeDisambiguatedBy<"BlezGroupBranch">; 74 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>, 75 DecodeDisambiguates<"BlezlGroupBranch">; 76 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>, 77 DecodeDisambiguatedBy<"BgtzGroupBranch">; 78 79 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>, 80 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 81 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>, 82 DecodeDisambiguatedBy<"BgtzGroupBranch">; 83 84 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>, 85 DecodeDisambiguatedBy<"BlezlGroupBranch">; 86 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>, 87 DecodeDisambiguates<"BgtzGroupBranch">; 88 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>, 89 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 90 91 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; 92 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>, 93 DecodeDisambiguates<"BlezGroupBranch">; 94 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; 95 96 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>; 97 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; 98 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; 99 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; 100 101 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; 102 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; 103 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>; 104 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; 105 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>, 106 DecodeDisambiguatedBy<"BlezGroupBranch">; 107 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 108 DecodeDisambiguatedBy<"DaddiGroupBranch">; 109 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 110 DecodeDisambiguatedBy<"AddiGroupBranch">; 111 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; 112 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; 113 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; 114 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; 115 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; 116 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; 117 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; 118 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; 119 120 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>; 121 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>; 122 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>; 123 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; 124 125 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; 126 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; 127 128 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>; 129 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; 130 131 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>; 132 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 133 134 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; 135 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; 136 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; 137 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; 138 139 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; 140 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; 141 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; 142 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; 143 144 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; 145 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; 146 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; 147 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; 148 149 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; 150 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; 151 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; 152 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; 153 154 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>; 155 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>; 156 157 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>; 158 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>; 159 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>; 160 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>; 161 162 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>; 163 164 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>; 165 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>; 166 167 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>; 168 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>; 169 170 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM; 171 172 //===----------------------------------------------------------------------===// 173 // 174 // Instruction Multiclasses 175 // 176 //===----------------------------------------------------------------------===// 177 178 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, 179 RegisterOperand FGROpnd, 180 SDPatternOperator Op = null_frag> { 181 dag OutOperandList = (outs FGRCCOpnd:$fd); 182 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 183 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); 184 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; 185 } 186 187 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, 188 RegisterOperand FGROpnd>{ 189 let AdditionalPredicates = [NotInMicroMips] in { 190 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>, 191 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, 192 ISA_MIPS32R6, HARDFLOAT; 193 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, 194 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, 195 ISA_MIPS32R6, HARDFLOAT; 196 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, 197 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, 198 ISA_MIPS32R6, HARDFLOAT; 199 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>, 200 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, 201 ISA_MIPS32R6, HARDFLOAT; 202 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, 203 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, 204 ISA_MIPS32R6, HARDFLOAT; 205 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>, 206 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, 207 ISA_MIPS32R6, HARDFLOAT; 208 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, 209 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, 210 ISA_MIPS32R6, HARDFLOAT; 211 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>, 212 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, 213 ISA_MIPS32R6, HARDFLOAT; 214 def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>, 215 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, 216 ISA_MIPS32R6, HARDFLOAT; 217 def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>, 218 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, 219 ISA_MIPS32R6, HARDFLOAT; 220 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>, 221 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, 222 ISA_MIPS32R6, HARDFLOAT; 223 def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>, 224 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, 225 ISA_MIPS32R6, HARDFLOAT; 226 def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>, 227 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, 228 ISA_MIPS32R6, HARDFLOAT; 229 def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>, 230 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, 231 ISA_MIPS32R6, HARDFLOAT; 232 def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>, 233 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, 234 ISA_MIPS32R6, HARDFLOAT; 235 def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>, 236 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, 237 ISA_MIPS32R6, HARDFLOAT; 238 } 239 } 240 241 //===----------------------------------------------------------------------===// 242 // 243 // Instruction Descriptions 244 // 245 //===----------------------------------------------------------------------===// 246 247 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 248 Operand ImmOpnd> : MipsR6Arch<instr_asm> { 249 dag OutOperandList = (outs GPROpnd:$rs); 250 dag InOperandList = (ins ImmOpnd:$imm); 251 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 252 list<dag> Pattern = []; 253 } 254 255 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>; 256 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>; 257 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>; 258 259 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 260 Operand ImmOpnd> : MipsR6Arch<instr_asm> { 261 dag OutOperandList = (outs GPROpnd:$rd); 262 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 263 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 264 list<dag> Pattern = []; 265 } 266 267 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>; 268 269 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 270 : MipsR6Arch<instr_asm> { 271 dag OutOperandList = (outs GPROpnd:$rs); 272 dag InOperandList = (ins simm16:$imm); 273 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 274 list<dag> Pattern = []; 275 } 276 277 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>; 278 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>; 279 280 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 281 : MipsR6Arch<instr_asm> { 282 dag OutOperandList = (outs GPROpnd:$rs); 283 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); 284 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); 285 list<dag> Pattern = []; 286 } 287 288 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>; 289 290 class BRANCH_DESC_BASE { 291 bit isBranch = 1; 292 bit isTerminator = 1; 293 bit hasDelaySlot = 0; 294 } 295 296 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE, 297 MipsR6Arch<instr_asm> { 298 dag InOperandList = (ins opnd:$offset); 299 dag OutOperandList = (outs); 300 string AsmString = !strconcat(instr_asm, "\t$offset"); 301 bit isBarrier = 1; 302 } 303 304 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 305 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 306 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 307 dag OutOperandList = (outs); 308 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 309 list<Register> Defs = [AT]; 310 } 311 312 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 313 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 314 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 315 dag OutOperandList = (outs); 316 string AsmString = !strconcat(instr_asm, "\t$rs, $offset"); 317 list<Register> Defs = [AT]; 318 } 319 320 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 321 RegisterOperand GPROpnd> 322 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> { 323 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 324 dag OutOperandList = (outs); 325 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 326 list<Register> Defs = [AT]; 327 } 328 329 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> { 330 bit isCall = 1; 331 bit hasDelaySlot = 1; 332 list<Register> Defs = [RA]; 333 } 334 335 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> { 336 bit isCall = 1; 337 list<Register> Defs = [RA]; 338 } 339 340 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>; 341 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>; 342 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>; 343 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>; 344 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>; 345 346 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>; 347 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>; 348 349 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>; 350 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>; 351 352 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>; 353 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>; 354 355 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>; 356 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>; 357 358 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 359 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset); 360 dag OutOperandList = (outs); 361 string AsmString = instr_asm; 362 bit hasDelaySlot = 1; 363 } 364 365 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">; 366 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">; 367 368 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 369 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset); 370 dag OutOperandList = (outs); 371 string AsmString = instr_asm; 372 bit hasDelaySlot = 1; 373 } 374 375 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; 376 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">; 377 378 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; 379 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; 380 381 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 382 RegisterOperand GPROpnd> 383 : MipsR6Arch<opstr> { 384 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 385 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 386 list<dag> Pattern = []; 387 bit isTerminator = 1; 388 bit hasDelaySlot = 0; 389 } 390 391 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 392 GPR32Opnd> { 393 bit isCall = 1; 394 list<Register> Defs = [RA]; 395 } 396 397 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> { 398 bit isBarrier = 1; 399 list<Register> Defs = [AT]; 400 } 401 402 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { 403 bit isBranch = 1; 404 bit isIndirectBranch = 1; 405 bit hasDelaySlot = 1; 406 bit isTerminator=1; 407 bit isBarrier=1; 408 } 409 410 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 411 : MipsR6Arch<instr_asm> { 412 dag OutOperandList = (outs GPROpnd:$rd); 413 dag InOperandList = (ins GPROpnd:$rt); 414 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 415 list<dag> Pattern = []; 416 } 417 418 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>; 419 420 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 421 SDPatternOperator Op=null_frag> 422 : MipsR6Arch<instr_asm> { 423 dag OutOperandList = (outs GPROpnd:$rd); 424 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 425 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 426 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 427 428 // This instruction doesn't trap division by zero itself. We must insert 429 // teq instructions as well. 430 bit usesCustomInserter = 1; 431 } 432 433 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>; 434 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>; 435 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>; 436 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>; 437 438 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { 439 list<Register> Defs = [RA]; 440 } 441 442 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { 443 list<Register> Defs = [RA]; 444 } 445 446 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { 447 list<Register> Defs = [RA]; 448 } 449 450 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { 451 list<Register> Defs = [RA]; 452 } 453 454 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { 455 list<Register> Defs = [RA]; 456 } 457 458 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { 459 list<Register> Defs = [RA]; 460 } 461 462 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 463 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> { 464 dag OutOperandList = (outs GPROpnd:$rd); 465 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 466 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 467 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))]; 468 } 469 470 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>; 471 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>; 472 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>; 473 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>; 474 475 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 476 dag OutOperandList = (outs FGROpnd:$fd); 477 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 478 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 479 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in, 480 FGROpnd:$ft, 481 FGROpnd:$fs))]; 482 string Constraints = "$fd_in = $fd"; 483 } 484 485 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> { 486 // We must insert a SUBREG_TO_REG around $fd_in 487 bit usesCustomInserter = 1; 488 } 489 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>; 490 491 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 492 : MipsR6Arch<instr_asm> { 493 dag OutOperandList = (outs GPROpnd:$rd); 494 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 495 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 496 list<dag> Pattern = []; 497 } 498 499 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>; 500 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>; 501 502 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 503 dag OutOperandList = (outs FGROpnd:$fd); 504 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 505 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 506 list<dag> Pattern = []; 507 string Constraints = "$fd_in = $fd"; 508 } 509 510 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>; 511 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>; 512 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>; 513 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>; 514 515 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 516 dag OutOperandList = (outs FGROpnd:$fd); 517 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 518 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 519 list<dag> Pattern = []; 520 } 521 522 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; 523 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; 524 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; 525 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; 526 527 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; 528 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; 529 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; 530 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; 531 532 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 533 dag OutOperandList = (outs FGROpnd:$fd); 534 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 535 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 536 list<dag> Pattern = []; 537 } 538 539 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; 540 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; 541 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; 542 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; 543 544 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 545 dag OutOperandList = (outs FGROpnd:$fd); 546 dag InOperandList = (ins FGROpnd:$fs); 547 string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); 548 list<dag> Pattern = []; 549 } 550 551 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; 552 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; 553 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; 554 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; 555 556 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, 557 RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> { 558 dag OutOperandList = (outs); 559 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 560 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 561 list<dag> Pattern = []; 562 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 563 } 564 565 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; 566 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>; 567 568 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 569 dag OutOperandList = (outs COPOpnd:$rt); 570 dag InOperandList = (ins mem_simm11:$addr); 571 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 572 list<dag> Pattern = []; 573 bit mayLoad = 1; 574 string DecoderMethod = "DecodeFMemCop2R6"; 575 } 576 577 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; 578 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>; 579 580 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { 581 dag OutOperandList = (outs); 582 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr); 583 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 584 list<dag> Pattern = []; 585 bit mayStore = 1; 586 string DecoderMethod = "DecodeFMemCop2R6"; 587 } 588 589 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; 590 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>; 591 592 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 593 Operand ImmOpnd> : MipsR6Arch<instr_asm> { 594 dag OutOperandList = (outs GPROpnd:$rd); 595 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); 596 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2"); 597 list<dag> Pattern = []; 598 } 599 600 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>; 601 602 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 603 dag OutOperandList = (outs GPROpnd:$rt); 604 dag InOperandList = (ins mem_simm9:$addr); 605 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 606 list<dag> Pattern = []; 607 bit mayLoad = 1; 608 } 609 610 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>; 611 612 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 613 dag OutOperandList = (outs GPROpnd:$dst); 614 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 615 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 616 list<dag> Pattern = []; 617 bit mayStore = 1; 618 string Constraints = "$rt = $dst"; 619 } 620 621 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>; 622 623 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> 624 : MipsR6Arch<instr_asm> { 625 dag OutOperandList = (outs GPROpnd:$rd); 626 dag InOperandList = (ins GPROpnd:$rs); 627 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 628 } 629 630 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : 631 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> { 632 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))]; 633 } 634 635 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : 636 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> { 637 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; 638 } 639 640 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>; 641 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>; 642 643 class SDBBP_R6_DESC { 644 dag OutOperandList = (outs); 645 dag InOperandList = (ins uimm20:$code_); 646 string AsmString = "sdbbp\t$code_"; 647 list<dag> Pattern = []; 648 } 649 650 //===----------------------------------------------------------------------===// 651 // 652 // Instruction Definitions 653 // 654 //===----------------------------------------------------------------------===// 655 656 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; 657 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; 658 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; 659 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6; 660 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; 661 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; 662 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; 663 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; 664 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; 665 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; 666 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; 667 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; 668 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; 669 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; 670 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; 671 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; 672 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; 673 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; 674 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; 675 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; 676 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; 677 def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; 678 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; 679 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; 680 def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; 681 def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; 682 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; 683 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; 684 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; 685 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; 686 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; 687 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; 688 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; 689 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; 690 let AdditionalPredicates = [NotInMicroMips] in { 691 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT; 692 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT; 693 } 694 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; 695 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; 696 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; 697 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; 698 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; 699 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; 700 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; 701 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; 702 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; 703 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; 704 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; 705 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; 706 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; 707 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; 708 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; 709 let AdditionalPredicates = [NotInMicroMips] in { 710 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 711 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 712 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 713 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 714 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT; 715 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT; 716 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT; 717 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT; 718 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT; 719 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT; 720 } 721 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6; 722 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6; 723 let AdditionalPredicates = [NotInMicroMips] in { 724 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT; 725 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT; 726 } 727 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; 728 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; 729 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; 730 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; 731 def NAL; // BAL with rd=0 732 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; 733 let AdditionalPredicates = [NotInMicroMips] in { 734 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; 735 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; 736 } 737 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; 738 let AdditionalPredicates = [NotInMicroMips] in { 739 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; 740 } 741 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; 742 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; 743 let AdditionalPredicates = [NotInMicroMips] in { 744 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; 745 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; 746 } 747 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32; 748 let AdditionalPredicates = [NotInMicroMips] in { 749 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; 750 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; 751 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; 752 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; 753 } 754 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; 755 756 //===----------------------------------------------------------------------===// 757 // 758 // Instruction Aliases 759 // 760 //===----------------------------------------------------------------------===// 761 762 let AdditionalPredicates = [NotInMicroMips] in { 763 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; 764 } 765 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6; 766 767 //===----------------------------------------------------------------------===// 768 // 769 // Patterns and Pseudo Instructions 770 // 771 //===----------------------------------------------------------------------===// 772 773 // comparisons supported via another comparison 774 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> { 775 def : MipsPat<(setone VT:$lhs, VT:$rhs), 776 (NOROp (!cast<Instruction>("CMP_UEQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 777 def : MipsPat<(seto VT:$lhs, VT:$rhs), 778 (NOROp (!cast<Instruction>("CMP_UN_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 779 def : MipsPat<(setune VT:$lhs, VT:$rhs), 780 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 781 def : MipsPat<(seteq VT:$lhs, VT:$rhs), 782 (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs)>; 783 def : MipsPat<(setgt VT:$lhs, VT:$rhs), 784 (!cast<Instruction>("CMP_LE_"#NAME) VT:$rhs, VT:$lhs)>; 785 def : MipsPat<(setge VT:$lhs, VT:$rhs), 786 (!cast<Instruction>("CMP_LT_"#NAME) VT:$rhs, VT:$lhs)>; 787 def : MipsPat<(setlt VT:$lhs, VT:$rhs), 788 (!cast<Instruction>("CMP_LT_"#NAME) VT:$lhs, VT:$rhs)>; 789 def : MipsPat<(setle VT:$lhs, VT:$rhs), 790 (!cast<Instruction>("CMP_LE_"#NAME) VT:$lhs, VT:$rhs)>; 791 def : MipsPat<(setne VT:$lhs, VT:$rhs), 792 (NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>; 793 } 794 795 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6; 796 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6; 797 798 // i32 selects 799 multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp, 800 Instruction SLTiOp, Instruction SLTiuOp, 801 Instruction SELEQZOp, Instruction SELNEZOp, 802 SDPatternOperator imm_type, ValueType Opg> { 803 // reg, immz 804 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, RC:$f), 805 (OROp (SELEQZOp RC:$t, RC:$cond), (SELNEZOp RC:$f, RC:$cond))>; 806 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, RC:$f), 807 (OROp (SELNEZOp RC:$t, RC:$cond), (SELEQZOp RC:$f, RC:$cond))>; 808 809 // reg, immZExt16[_64] 810 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 811 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 812 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 813 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f), 814 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)), 815 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>; 816 817 // reg, immSExt16Plus1 818 def : MipsPat<(select (Opg (setgt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 819 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))), 820 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>; 821 def : MipsPat<(select (Opg (setugt RC:$cond, immSExt16Plus1:$imm)), RC:$t, RC:$f), 822 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))), 823 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>; 824 825 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), RC:$t, immz), 826 (SELEQZOp RC:$t, RC:$cond)>; 827 def : MipsPat<(select (Opg (setne RC:$cond, immz)), RC:$t, immz), 828 (SELNEZOp RC:$t, RC:$cond)>; 829 def : MipsPat<(select (Opg (seteq RC:$cond, immz)), immz, RC:$f), 830 (SELNEZOp RC:$f, RC:$cond)>; 831 def : MipsPat<(select (Opg (setne RC:$cond, immz)), immz, RC:$f), 832 (SELEQZOp RC:$f, RC:$cond)>; 833 } 834 835 defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ, 836 immZExt16, i32>, ISA_MIPS32R6; 837 838 def : MipsPat<(select i32:$cond, i32:$t, i32:$f), 839 (OR (SELNEZ i32:$t, i32:$cond), 840 (SELEQZ i32:$f, i32:$cond))>, 841 ISA_MIPS32R6; 842 def : MipsPat<(select i32:$cond, i32:$t, immz), 843 (SELNEZ i32:$t, i32:$cond)>, 844 ISA_MIPS32R6; 845 def : MipsPat<(select i32:$cond, immz, i32:$f), 846 (SELEQZ i32:$f, i32:$cond)>, 847 ISA_MIPS32R6; 848
