| /external/llvm/test/CodeGen/Mips/cconv/ |
| callee-saved-fpxx.ll | 52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
53 ; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
54 ; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
55 ; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
56 ; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
57 ; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
|
| return-hard-float.ll | 46 ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
47 ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
49 ; N64-DAG: ldc1 $f0, 0([[R1]])
58 ; 032FP64-DAG: ldc1 $f0, 0($sp)
59 ; 032FP64-DAG: ldc1 $f2, 8($sp)
|
| arguments-hard-float.ll | 62 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 16($sp)
65 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 24($sp)
68 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 32($sp)
71 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 40($sp)
74 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 48($sp)
77 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 56($sp)
82 ; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 64($sp)
84 ; NEW-DAG: ldc1 [[F1:\$f[0-9]+]], 0($sp)
|
| callee-saved-fpxx1.ll | 22 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
|
| /external/llvm/test/CodeGen/Mips/ |
| select.ll | 170 ; 32-DAG: ldc1 $[[F1:f0]], 16($sp)
175 ; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp)
182 ; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp)
352 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
353 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
358 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
359 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
364 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
365 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
389 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp
[all...] |
| fp-indexed-ls.ll | 59 ; MIPS32R1: ldc1 $f0, 0($[[T3]])
66 ; MIPS32R6: ldc1 $f0, 0($[[T3]])
75 ; MIPS64R6: ldc1 $f0, 0($[[T3]])
142 ; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
146 ; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
149 ; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
153 ; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
156 ; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
|
| o32_cc.ll | 9 ; ALL-DAG: ldc1 $f12, %lo
10 ; ALL-DAG: ldc1 $f14, %lo
34 ; ALL-DAG: ldc1 $f14, %lo
45 ; ALL-DAG: ldc1 $f12, %lo
71 ; ALL-DAG: ldc1 $f12, %lo
85 ; ALL-DAG: ldc1 $f12, %lo
205 ; ALL-DAG: ldc1 $f12, %lo
328 ; ALL-DAG: ldc1 $f12, %lo
340 ; ALL-DAG: ldc1 $f12, %lo
|
| fp64a.ll | 44 ; 32R2-FP64A: ldc1 $f0, 0($sp)
64 ; 32R2-FP64A: ldc1 $f0, 0($sp)
84 ; 32R2-FP64A: ldc1 $f0, 0($sp)
104 ; 32R2-FP64A: ldc1 $f0, 0($sp)
131 ; 32R2-FP64A: ldc1 $[[T1:f[0-9]+]], 0($sp)
134 ; 32R2-FP64A: ldc1 $[[T0:f[0-9]+]], 0($sp)
|
| mips64fpldst.ll | 27 ; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
30 ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
|
| fastcc.ll | 362 ; FP64-NOODDSPREG-DAG: ldc1 $f0, 0($[[R0]])
363 ; FP64-NOODDSPREG-DAG: ldc1 $f2, 8($[[R0]])
364 ; FP64-NOODDSPREG-DAG: ldc1 $f4, 16($[[R0]])
365 ; FP64-NOODDSPREG-DAG: ldc1 $f6, 24($[[R0]])
366 ; FP64-NOODDSPREG-DAG: ldc1 $f8, 32($[[R0]])
367 ; FP64-NOODDSPREG-DAG: ldc1 $f10, 40($[[R0]])
368 ; FP64-NOODDSPREG-DAG: ldc1 $f12, 48($[[R0]])
369 ; FP64-NOODDSPREG-DAG: ldc1 $f14, 56($[[R0]])
370 ; FP64-NOODDSPREG-DAG: ldc1 $f16, 64($[[R0]])
371 ; FP64-NOODDSPREG-DAG: ldc1 $f18, 72($[[R0]]
[all...] |
| fpxx.ll | 35 ; 32-FPXX: ldc1 $f0, 0($sp)
60 ; 32-FPXX: ldc1 $f0, 0($sp)
84 ; 32-FPXX: ldc1 $f0, 0($sp)
108 ; 32-FPXX: ldc1 $f0, 0($sp)
132 ; 32-FPXX: ldc1 $f0, 0($sp)
160 ; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
163 ; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
|
| fmadd1.ll | 191 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
197 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
203 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
232 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
238 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
244 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
273 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
279 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
282 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
288 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp
[all...] |
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| fpcmpa.ll | 143 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
144 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
163 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
164 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
183 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
184 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
203 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
204 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
223 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
224 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| l_d-n64.d | 11 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(zero\)
12 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(zero\)
14 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
15 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(zero\)
17 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(at\)
19 [0-9a-f]+ <[^>]*> ldc1 \$f4,-23131\(at\)
20 [0-9a-f]+ <[^>]*> ldc1 \$f4,0\(a1\)
21 [0-9a-f]+ <[^>]*> ldc1 \$f4,1\(a1\)
24 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(at\)
25 [0-9a-f]+ <[^>]*> ldc1 \$f4,-32768\(a1\
[all...] |
| mips-macro-ill-nofp.l | 2 .*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
3 .*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
| mips-gp32-fp64.d | 68 e4: d7800000 ldc1 \$f0,0\(gp\)
69 e8: d7800008 ldc1 \$f0,8\(gp\)
|
| mips-gp32-fp64.s | 72 li.d $f0, 1.0 # 00e4 ldc1 $f0,L1.0(gp)
73 li.d $f0, 1.9 # 00e8 ldc1 $f0,L1.9(gp)
|
| li-d.d | 19 [0-9a-f]+ <[^>]*> ldc1 \$f0,0\(gp\)
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| mips16-intermix-1.s | 97 ldc1 $f22,48($sp)
98 ldc1 $f20,40($sp)
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2-wrong-error.s | 9 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips3-wrong-error.s | 10 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips4-wrong-error.s | 12 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/v8/test/cctest/ |
| test-assembler-mips64.cc | 291 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
292 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) );
317 __ ldc1(f4, MemOperand(a0, offsetof(T, h)) );
318 __ ldc1(f6, MemOperand(a0, offsetof(T, i)) );
414 __ ldc1(f4, MemOperand(a0, offsetof(T, a)));
415 __ ldc1(f5, MemOperand(a0, offsetof(T, b)));
434 __ ldc1(f4, MemOperand(a0, offsetof(T, d)));
482 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
483 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) );
629 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) )
[all...] |
| test-assembler-mips.cc | 282 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
283 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) );
308 __ ldc1(f4, MemOperand(a0, offsetof(T, h)) );
309 __ ldc1(f6, MemOperand(a0, offsetof(T, i)) );
402 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
403 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) );
470 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
471 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) );
619 __ ldc1(f4, MemOperand(a0, offsetof(T, a)) );
620 __ ldc1(f6, MemOperand(a0, offsetof(T, b)) )
[all...] |
| /external/v8/src/crankshaft/mips64/ |
| lithium-gap-resolver-mips64.cc | 153 __ ldc1(kLithiumScratchDouble, cgen_->ToMemOperand(source));
214 __ ldc1(kLithiumScratchDouble, source_operand);
269 __ ldc1(cgen_->ToDoubleRegister(destination), source_operand);
285 __ ldc1(kLithiumScratchDouble, source_operand);
|
