| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| ld.s | 27 # If defined, test ldc1 instead.
31 ldc1 \ops
|
| mips-gp32-fp64-pic.d | 89 138: d4200008 ldc1 \$f0,8\(at\)
91 140: d4200010 ldc1 \$f0,16\(at\)
|
| mips-gp32-fp64-pic.s | 114 # 0180 ldc1 $f0,lo(L1.0)(at)
116 # 0188 ldc1 $f0,lo(L1.9)(at)
|
| mips-abi32.d | 70 f0: d7800000 ldc1 \$f0,0\(gp\)
|
| mips-abi32.s | 75 li.d $f0, 1.9 # 00f0 ldc1 $f0,L1.9(gp)
|
| mips-gp32-fp32.d | 70 f0: d7800000 ldc1 \$f0,0\(gp\)
|
| mips-gp32-fp32.s | 75 li.d $f0, 1.9 # 00f0 ldc1 $f0,L1.9(gp)
|
| mips-abi32-pic.d | 91 144: d4200008 ldc1 \$f0,8\(at\)
|
| /external/clang/test/Driver/ |
| mips-features.c | 133 // RUN: -mno-ldc1-sdc1 -mldc1-sdc1 2>&1 \
135 // CHECK-LDC1SDC1-NOT: "-mllvm" "-mno-ldc1-sdc1"
137 // -mno-ldc1-sdc1
139 // RUN: -mldc1-sdc1 -mno-ldc1-sdc1 2>&1 \
141 // CHECK-NOLDC1SDC1: "-mllvm" "-mno-ldc1-sdc1"
|
| /external/llvm/test/CodeGen/Mips/ |
| o32_cc_vararg.ll | 65 ; CHECK: ldc1 $f0, 0($[[R3]])
112 ; CHECK: ldc1 $f0, 32($sp)
168 ; CHECK: ldc1 $f0, 0($[[R3]])
215 ; CHECK: ldc1 $f0, 48($sp)
269 ; CHECK: ldc1 $f0, 0($[[R3]])
|
| return-vector.ll | 84 ; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp)
85 ; CHECK: ldc1 $[[R1:[a-z0-9]+]], 48($sp)
86 ; CHECK: ldc1 $[[R3:[a-z0-9]+]], 40($sp)
87 ; CHECK: ldc1 $[[R4:[a-z0-9]+]], 32($sp)
146 ; CHECK-NOT: ldc1
|
| no-odd-spreg-msa.ll | 41 ; ALL-NOT: ldc1
75 ; ALL-NOT: ldc1
|
| /external/v8/src/crankshaft/mips/ |
| lithium-gap-resolver-mips.cc | 153 __ ldc1(kLithiumScratchDouble, cgen_->ToMemOperand(source));
268 __ ldc1(cgen_->ToDoubleRegister(destination), source_operand);
284 __ ldc1(kLithiumScratchDouble, source_operand);
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| loadstore2.ll | 77 ; CHECK: ldc1 $f[[REGd:[0-9]+]], 0(${{[0-9]+}})
|
| retabi.ll | 106 ; CHECK: ldc1 $f0, 0($[[REG_D_ADDR]])
|
| sel1.ll | 89 ; CHECK-DAG: ldc1 $f0, 16($sp)
|
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 702 TEST_F(AssemblerMIPSTest, Ldc1) {
703 DriverStr(RepeatFRIb(&mips::MipsAssembler::Ldc1, -16, "ldc1 ${reg1}, {imm}(${reg2})"), "Ldc1");
[all...] |
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float-varargs.ll | 87 ; O32-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 16($sp)
88 ; NEW-DAG: ldc1 [[FTMP1:\$f[0-9]+]], 8($sp)
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ret.ll | 202 ; O32-DAG: ldc1 $f0, %lo($CPI
203 ; N64-DAG: ldc1 $f0, %got_ofst($CPI
|
| /external/llvm/test/MC/Mips/ |
| nacl-mask.s | 50 ldc1 $f2, 0($7)
85 # CHECK-NEXT: ldc1 $f2, 0($7)
|
| /external/v8/src/mips/ |
| codegen-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| codegen-mips64.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrFPU.td | 23 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
|
| /external/v8/test/cctest/ |
| test-code-stubs-mips.cc | 100 __ ldc1(f12, MemOperand(source_reg));
|
| test-code-stubs-mips64.cc | 100 __ ldc1(f12, MemOperand(source_reg));
|
