| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/lm32/ |
| insn.d | 238 390: 2c 00 00 00 lhu r0,\(r0\+0\)
239 394: 2c 41 00 03 lhu r1,\(r2\+3\)
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| microblaze-opc.h | 229 {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
[all...] |
| dlx-dis.c | 198 { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
|
| iq2000-desc.c | 855 /* lhu $rt,$lo16($base) */
857 IQ2000_INSN_LHU, "lhu", "lhu", 32,
[all...] |
| score-dis.c | 271 {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
273 {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
275 {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
[all...] |
| score-opc.h | 250 {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
252 {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
254 {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
|
| score7-dis.c | 297 {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"},
299 {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"},
301 {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"},
[all...] |
| /external/v8/src/regexp/mips/ |
| regexp-macro-assembler-mips.cc | 404 __ lhu(a3, MemOperand(a0, 0));
406 __ lhu(t0, MemOperand(a2, 0));
[all...] |
| /external/v8/src/regexp/mips64/ |
| regexp-macro-assembler-mips64.cc | 434 __ lhu(a3, MemOperand(a0, 0));
436 __ lhu(a4, MemOperand(a2, 0));
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPS64Assembler.cpp | 897 mMips->LHU(Rd, Rn, amode.value);
900 mMips->LHU(Rd, Rn, 0);
910 mMips->LHU(Rd, R_at, 0);
[all...] |
| MIPSAssembler.cpp | 905 mMips->LHU(Rd, Rn, amode.value);
908 mMips->LHU(Rd, Rn, 0);
918 mMips->LHU(Rd, R_at, 0);
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| iq2000.cpu | 246 ("LB" 32) ("LH" 33) ("LW" 35) ("LBU" 36) ("LHU" 37) ("RAM" 39)
1018 (dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT)
1019 "lhu $rt,$lo16($base)"
[all...] |
| mep-core.cpu | [all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 46 0xbd 0xa6 0x53 0x94 # CHECK: lhu $19, -22851($2)
|
| valid-mips1.txt | 104 0x94 0x53 0xa6 0xbd # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 59 0xbd 0xa6 0x53 0x94 # CHECK: lhu $19, -22851($2)
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 71 lhu $s3,-22851($v0)
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| callabi.ll | 265 ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
271 ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| row_mips.cc | 601 "lhu $t1, 0(%[u_buf]) \n" \
602 "lhu $t2, 0(%[v_buf]) \n" \
[all...] |
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | [all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 364 LHU = ((4U << 3) + 5) << kOpcodeShift,
901 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
[all...] |
| disasm-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 352 LHU = ((4U << 3) + 5) << kOpcodeShift,
948 OpcodeToBitNumber(LD) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 190 void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
|
| /art/disassembler/ |
| disassembler_mips.cc | 312 { kITypeMask, 37u << kOpcodeShift, "lhu", "TO", },
|
