1 ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ 2 ; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ 3 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 4 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ 5 ; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ 6 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 7 8 declare void @xb(i8) 9 10 define void @cxb() { 11 ; ALL-LABEL: cxb: 12 13 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 14 15 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24 16 ; 32R1: sra $4, $[[T1]], 24 17 18 ; 32R2: seb $4, $[[T0]] 19 call void @xb(i8 10) 20 ret void 21 } 22 23 declare void @xh(i16) 24 25 define void @cxh() { 26 ; ALL-LABEL: cxh: 27 28 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 29 30 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16 31 ; 32R1: sra $4, $[[T1]], 16 32 33 ; 32R2: seh $4, $[[T0]] 34 call void @xh(i16 10) 35 ret void 36 } 37 38 declare void @xi(i32) 39 40 define void @cxi() { 41 ; ALL-LABEL: cxi: 42 43 ; ALL-DAG: addiu $4, $zero, 10 44 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}}) 45 ; ALL: jalr $25 46 call void @xi(i32 10) 47 ret void 48 } 49 50 declare void @xbb(i8, i8) 51 52 define void @cxbb() { 53 ; ALL-LABEL: cxbb: 54 55 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 56 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 57 58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24 59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24 60 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24 62 63 ; 32R2-DAG: seb $4, $[[T0]] 64 ; 32R2-DAG: seb $5, $[[T1]] 65 call void @xbb(i8 76, i8 101) 66 ret void 67 } 68 69 declare void @xhh(i16, i16) 70 71 define void @cxhh() { 72 ; ALL-LABEL: cxhh: 73 74 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 75 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 76 77 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16 78 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16 79 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 80 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16 81 82 ; 32R2-DAG: seh $4, $[[T0]] 83 ; 32R2-DAG: seh $5, $[[T1]] 84 call void @xhh(i16 76, i16 101) 85 ret void 86 } 87 88 declare void @xii(i32, i32) 89 90 define void @cxii() { 91 ; ALL-LABEL: cxii: 92 93 ; ALL-DAG: addiu $4, $zero, 746 94 ; ALL-DAG: addiu $5, $zero, 892 95 ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}}) 96 ; ALL: jalr $25 97 call void @xii(i32 746, i32 892) 98 ret void 99 } 100 101 declare void @xccc(i8, i8, i8) 102 103 define void @cxccc() { 104 ; ALL-LABEL: cxccc: 105 106 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 107 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 108 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 109 110 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24 111 ; 32R1-DAG: sra $4, $[[T3]], 24 112 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 113 ; 32R1-DAG: sra $5, $[[T4]], 24 114 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24 115 ; 32R1-DAG: sra $6, $[[T5]], 24 116 117 ; 32R2-DAG: seb $4, $[[T0]] 118 ; 32R2-DAG: seb $5, $[[T1]] 119 ; 32R2-DAG: seb $6, $[[T2]] 120 call void @xccc(i8 88, i8 44, i8 11) 121 ret void 122 } 123 124 declare void @xhhh(i16, i16, i16) 125 126 define void @cxhhh() { 127 ; ALL-LABEL: cxhhh: 128 129 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 130 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 131 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 132 133 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16 134 ; 32R1-DAG: sra $4, $[[T3]], 16 135 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 136 ; 32R1-DAG: sra $5, $[[T4]], 16 137 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16 138 ; 32R1-DAG: sra $6, $[[T5]], 16 139 140 ; 32R2-DAG: seh $4, $[[T0]] 141 ; 32R2-DAG: seh $5, $[[T1]] 142 ; 32R2-DAG: seh $6, $[[T2]] 143 call void @xhhh(i16 88, i16 44, i16 11) 144 ret void 145 } 146 147 declare void @xiii(i32, i32, i32) 148 149 define void @cxiii() { 150 ; ALL-LABEL: cxiii: 151 152 ; ALL-DAG: addiu $4, $zero, 88 153 ; ALL-DAG: addiu $5, $zero, 44 154 ; ALL-DAG: addiu $6, $zero, 11 155 ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}}) 156 ; ALL: jalr $25 157 call void @xiii(i32 88, i32 44, i32 11) 158 ret void 159 } 160 161 declare void @xcccc(i8, i8, i8, i8) 162 163 define void @cxcccc() { 164 ; ALL-LABEL: cxcccc: 165 166 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 167 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 168 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 169 ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33 170 171 ; FIXME: We should avoid the unnecessary spill/reload here. 172 173 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24 174 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24 175 ; 32R1-DAG: sw $4, 16($sp) 176 ; 32R1-DAG: move $4, $[[T5]] 177 ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24 178 ; 32R1-DAG: sra $5, $[[T6]], 24 179 ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24 180 ; 32R1-DAG: sra $6, $[[T7]], 24 181 ; 32R1: lw $[[T8:[0-9]+]], 16($sp) 182 ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24 183 ; 32R1: sra $7, $[[T9]], 24 184 185 ; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]] 186 ; 32R2-DAG: sw $4, 16($sp) 187 ; 32R2-DAG: move $4, $[[T4]] 188 ; 32R2-DAG: seb $5, $[[T1]] 189 ; 32R2-DAG: seb $6, $[[T2]] 190 ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp) 191 ; 32R2: seb $7, $[[T5]] 192 call void @xcccc(i8 88, i8 44, i8 11, i8 33) 193 ret void 194 } 195 196 declare void @xhhhh(i16, i16, i16, i16) 197 198 define void @cxhhhh() { 199 ; ALL-LABEL: cxhhhh: 200 201 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 202 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 203 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 204 ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33 205 206 ; FIXME: We should avoid the unnecessary spill/reload here. 207 208 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16 209 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16 210 ; 32R1-DAG: sw $4, 16($sp) 211 ; 32R1-DAG: move $4, $[[T5]] 212 ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16 213 ; 32R1-DAG: sra $5, $[[T6]], 16 214 ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16 215 ; 32R1-DAG: sra $6, $[[T7]], 16 216 ; 32R1: lw $[[T8:[0-9]+]], 16($sp) 217 ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16 218 ; 32R1: sra $7, $[[T9]], 16 219 220 ; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]] 221 ; 32R2-DAG: sw $4, 16($sp) 222 ; 32R2-DAG: move $4, $[[T4]] 223 ; 32R2-DAG: seh $5, $[[T1]] 224 ; 32R2-DAG: seh $6, $[[T2]] 225 ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp) 226 ; 32R2: seh $7, $[[T5]] 227 call void @xhhhh(i16 88, i16 44, i16 11, i16 33) 228 ret void 229 } 230 231 declare void @xiiii(i32, i32, i32, i32) 232 233 define void @cxiiii() { 234 ; ALL-LABEL: cxiiii: 235 236 ; ALL-DAG: addiu $4, $zero, 167 237 ; ALL-DAG: addiu $5, $zero, 320 238 ; ALL-DAG: addiu $6, $zero, 97 239 ; ALL-DAG: addiu $7, $zero, 14 240 ; ALL-DAG: lw $25, %got(xiiii)(${{[0-9]+}}) 241 ; ALL: jalr $25 242 call void @xiiii(i32 167, i32 320, i32 97, i32 14) 243 ret void 244 } 245 246 @c1 = global i8 -45, align 1 247 @uc1 = global i8 27, align 1 248 @s1 = global i16 -1789, align 2 249 @us1 = global i16 1256, align 2 250 251 define void @cxiiiiconv() { 252 ; ALL-LABEL: cxiiiiconv: 253 254 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 255 ; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]]) 256 ; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]]) 257 ; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24 258 ; 32R1-DAG: sra $4, $[[REG_C1_1]], 24 259 ; 32R2-DAG: seb $4, $[[REG_C1]] 260 ; FIXME: andi is superfulous 261 ; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) 262 ; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]]) 263 ; ALL-DAG: andi $5, $[[REG_UC1]], 255 264 ; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) 265 ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]]) 266 ; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16 267 ; 32R1-DAG: sra $6, $[[REG_S1_1]], 16 268 ; 32R2-DAG: seh $6, $[[REG_S1]] 269 ; FIXME andi is superfulous 270 ; ALL-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) 271 ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]]) 272 ; ALL-DAG: andi $7, $[[REG_US1]], 65535 273 ; ALL: jalr $25 274 %1 = load i8, i8* @c1, align 1 275 %conv = sext i8 %1 to i32 276 %2 = load i8, i8* @uc1, align 1 277 %conv1 = zext i8 %2 to i32 278 %3 = load i16, i16* @s1, align 2 279 %conv2 = sext i16 %3 to i32 280 %4 = load i16, i16* @us1, align 2 281 %conv3 = zext i16 %4 to i32 282 call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3) 283 ret void 284 } 285 286 declare void @xf(float) 287 288 define void @cxf() { 289 ; ALL-LABEL: cxf: 290 291 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 292 ; ALL: lui $[[REG_FPCONST_1:[0-9]+]], 17886 293 ; ALL: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067 294 ; ALL: mtc1 $[[REG_FPCONST]], $f12 295 ; ALL: lw $25, %got(xf)($[[REG_GP]]) 296 ; ALL: jalr $25 297 call void @xf(float 0x40BBC85560000000) 298 ret void 299 } 300 301 declare void @xff(float, float) 302 303 define void @cxff() { 304 ; ALL-LABEL: cxff: 305 306 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 307 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314 308 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349 309 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 310 ; ALL-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593 311 ; ALL-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642 312 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14 313 ; ALL-DAG: lw $25, %got(xff)($[[REG_GP]]) 314 ; ALL: jalr $25 315 call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000) 316 ret void 317 } 318 319 declare void @xfi(float, i32) 320 321 define void @cxfi() { 322 ; ALL-LABEL: cxfi: 323 324 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 325 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540 326 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554 327 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 328 ; ALL-DAG: addiu $5, $zero, 102 329 ; ALL-DAG: lw $25, %got(xfi)($[[REG_GP]]) 330 ; ALL: jalr $25 331 call void @xfi(float 0x4013906240000000, i32 102) 332 ret void 333 } 334 335 declare void @xfii(float, i32, i32) 336 337 define void @cxfii() { 338 ; ALL-LABEL: cxfii: 339 340 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 341 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142 342 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240 343 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 344 ; ALL-DAG: addiu $5, $zero, 9993 345 ; ALL-DAG: addiu $6, $zero, 10922 346 ; ALL-DAG: lw $25, %got(xfii)($[[REG_GP]]) 347 ; ALL: jalr $25 348 call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922) 349 ret void 350 } 351 352 declare void @xfiii(float, i32, i32, i32) 353 354 define void @cxfiii() { 355 ; ALL-LABEL: cxfiii: 356 357 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 358 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120 359 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681 360 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 361 ; ALL-DAG: addiu $5, $zero, 3948 362 ; ALL-DAG: lui $[[REG_I_1:[0-9]+]], 1 363 ; ALL-DAG: ori $6, $[[REG_I_1]], 23475 364 ; ALL-DAG: lui $[[REG_I_2:[0-9]+]], 1 365 ; ALL-DAG: ori $7, $[[REG_I_2]], 45686 366 ; ALL-DAG: lw $25, %got(xfiii)($[[REG_GP]]) 367 ; ALL: jalr $25 368 call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222) 369 ret void 370 } 371 372 declare void @xd(double) 373 374 define void @cxd() { 375 ; ALL-LABEL: cxd: 376 377 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 378 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514 379 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037 380 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195 381 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439 382 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 383 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 384 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 385 ; ALL-DAG: lw $25, %got(xd)($[[REG_GP]]) 386 ; ALL: jalr $25 387 call void @xd(double 5.994560e+02) 388 ret void 389 } 390 391 declare void @xdd(double, double) 392 393 define void @cxdd() { 394 ; ALL-LABEL: cxdd: 395 396 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 397 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531 398 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435 399 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078 400 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186 401 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 402 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 403 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 404 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629 405 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873 406 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438 407 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575 408 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f14 409 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f15 410 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14 411 ; ALL-DAG: lw $25, %got(xdd)($[[REG_GP]]) 412 ; ALL: jalr $25 413 call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917) 414 ret void 415 } 416 417 declare void @xif(i32, float) 418 419 define void @cxif() { 420 ; ALL-LABEL: cxif: 421 422 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 423 ; ALL-DAG: addiu $4, $zero, 345 424 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17374 425 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393 426 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 427 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 428 ; ALL-DAG: lw $25, %got(xif)($[[REG_GP]]) 429 ; ALL: jalr $25 430 call void @xif(i32 345, float 0x407BCE5A20000000) 431 ret void 432 } 433 434 declare void @xiff(i32, float, float) 435 436 define void @cxiff() { 437 ; ALL-LABEL: cxiff: 438 439 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 440 ; ALL-DAG: addiu $4, $zero, 12239 441 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526 442 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706 443 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 444 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543 445 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326 446 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 447 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 448 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] 449 ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]]) 450 ; ALL: jalr $25 451 call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000) 452 ret void 453 } 454 455 declare void @xifi(i32, float, i32) 456 457 define void @cxifi() { 458 ; ALL-LABEL: cxifi: 459 460 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 461 ; ALL-DAG: addiu $4, $zero, 887 462 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 16659 463 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759 464 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 465 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 466 ; ALL-DAG: addiu $6, $zero, 888 467 ; ALL-DAG: lw $25, %got(xifi)($[[REG_GP]]) 468 ; ALL: jalr $25 469 call void @xifi(i32 887, float 0x402277CEE0000000, i32 888) 470 ret void 471 } 472 473 declare void @xifif(i32, float, i32, float) 474 475 define void @cxifif() { 476 ; ALL-LABEL: cxifif: 477 478 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 479 ; ALL-DAG: lui $[[REGI:[0-9]+]], 1 480 ; ALL-DAG: ori $4, $[[REGI]], 2238 481 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527 482 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015 483 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 484 ; ALL-DAG: addiu $6, $zero, 9991 485 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802 486 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470 487 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 488 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 489 ; ALL-DAG: mfc1 $7, $f[[REGF1_3]] 490 ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]]) 491 ; ALL: jalr $25 492 call void @xifif(i32 67774, float 0x408EE0FBE0000000, 493 i32 9991, float 0x40B15C8CC0000000) 494 ret void 495 } 496 497 declare void @xiffi(i32, float, float, i32) 498 499 define void @cxiffi() { 500 ; ALL-LABEL: cxiffi: 501 502 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 503 ; ALL-DAG: addiu $4, $zero, 45 504 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307 505 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107 506 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] 507 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529 508 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322 509 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] 510 ; ALL-DAG: addiu $7, $zero, 234 511 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] 512 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] 513 ; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]]) 514 ; ALL: jalr $25 515 call void @xiffi(i32 45, float 0x3FF6666660000000, 516 float 0x408F333340000000, i32 234) 517 ret void 518 } 519 520 declare void @xifii(i32, float, i32, i32) 521 522 define void @cxifii() { 523 ; ALL-LABEL: cxifii: 524 525 ; ALL-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} 526 ; ALL-DAG: addiu $4, $zero, 12239 527 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17526 528 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706 529 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] 530 ; ALL-DAG: mfc1 $5, $f[[REGF_3]] 531 ; ALL-DAG: lui $[[REGI2:[0-9]+]], 15 532 ; ALL-DAG: ori $6, $[[REGI2]], 15837 533 ; ALL-DAG: addiu $7, $zero, 1234 534 ; ALL-DAG: lw $25, %got(xifii)($[[REG_GP]]) 535 ; ALL: jalr $25 536 call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234) 537 ret void 538 } 539
