| /external/llvm/test/CodeGen/MIR/X86/ |
| liveout-register-mask.mir | 19 liveins:
31 liveins: %rdi, %rsi, %rbp
|
| expected-named-register-in-allocation-hint.mir | 22 liveins: %edi, %esi
|
| simple-register-allocation-hints.mir | 27 liveins: %edi, %esi
|
| subregister-operands.mir | 23 liveins: %edi
|
| external-symbol-operands.mir | 35 liveins: %edi
46 liveins: %eax
|
| frame-info-stack-references.mir | 56 liveins: %rbx, %rbx
71 liveins: %eax
|
| virtual-registers.mir | 47 liveins: %edi
82 liveins: %edi
|
| cfi-offset.mir | 31 liveins: %ecx, %edi, %edx, %esi, %rbx
|
| instructions-debug-location.mir | 64 liveins: %edi
86 liveins: %edi
|
| expected-stack-object.mir | 52 liveins: %rbx, %rbx
|
| /external/llvm/test/CodeGen/X86/ |
| patchpoint-verifiable.mir | 19 liveins:
31 liveins: %rdi, %rsi, %rbp
|
| expand-vr64-gr64-copy.mir | 23 liveins: %xmm0
|
| /external/llvm/test/CodeGen/MIR/ARM/ |
| cfi-same-value.mir | 32 liveins: %r11, %lr
46 liveins: %r11, %lr
60 liveins: %r11, %lr
|
| ARMLoadStoreDBG.mir | 87 liveins:
127 liveins: %r0, %r2, %r3, %lr, %r7
137 liveins: %lr, %r7
145 liveins: %r0, %r2, %r3, %r7, %lr
|
| /external/llvm/test/CodeGen/MIR/AArch64/ |
| cfi-def-cfa.mir | 20 liveins: %lr, %fp, %lr, %fp
|
| multiple-lhs-operands.mir | 20 liveins: %lr, %fp, %lr, %fp
|
| /external/llvm/test/CodeGen/MIR/AMDGPU/ |
| target-index-operands.mir | 46 liveins:
52 liveins: %sgpr0_sgpr1
77 liveins:
83 liveins: %sgpr0_sgpr1
|
| expected-target-index-name.mir | 37 liveins:
43 liveins: %sgpr0_sgpr1
|
| invalid-target-index-operand.mir | 37 liveins:
43 liveins: %sgpr0_sgpr1
|
| /external/llvm/test/CodeGen/MIR/Mips/ |
| memory-operands.mir | 31 liveins:
44 liveins: %a0, %ra
80 liveins: %ra, %s2, %s0, %ra, %s2, %s0
|
| /external/llvm/test/DebugInfo/MIR/X86/ |
| live-debug-values-3preds.mir | 165 liveins:
187 liveins: %ecx, %edi, %edx, %esi
201 liveins: %ecx, %edi, %edx, %esi, %r8d
212 liveins: %eax, %ecx, %edi, %edx, %esi, %r8d
224 liveins: %eax, %ecx, %edi, %edx, %esi, %r8d
236 liveins: %eax, %ecx, %edi, %edx, %esi, %r8d
248 liveins: %eax, %ecx, %edi, %edx, %esi, %r8d
262 liveins: %ecx, %edi
273 liveins: %ecx, %esi
285 liveins: %ecx, %ed
[all...] |
| live-debug-values.mir | 168 liveins:
194 liveins: %edi, %rsi, %rbx
209 liveins: %rsi
220 liveins: %edi
230 liveins: %ebx
241 liveins: %ebx
249 liveins: %ecx
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 118 for (auto &I : LiveIns)
372 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
373 if (LiveIns[i].second) {
374 if (use_empty(LiveIns[i].second)) {
380 LiveIns.erase(LiveIns.begin() + i);
385 TII.get(TargetOpcode::COPY), LiveIns[i].second)
386 .addReg(LiveIns[i].first);
389 EntryMBB->addLiveIn(LiveIns[i].first);
393 EntryMBB->addLiveIn(LiveIns[i].first)
[all...] |
| MachineBasicBlock.cpp | 337 LiveIns.begin(), LiveIns.end(),
339 if (I == LiveIns.end())
344 LiveIns.erase(I);
349 LiveIns.begin(), LiveIns.end(),
355 std::sort(LiveIns.begin(), LiveIns.end(),
359 // Liveins are sorted by physreg now we can merge their lanemasks.
360 LiveInVector::const_iterator I = LiveIns.begin()
[all...] |
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIParser.h | 61 /// instructions and basic block attributes like liveins and successors.
|
