| /external/llvm/test/CodeGen/AArch64/ |
| aarch64-2014-08-11-MachineCombinerCrash.ll | 25 %shr83351 = lshr i64 %add82, 11, !dbg !58
31 %shr89352 = lshr i64 %add88, 11, !dbg !59
|
| arm64-rev.ll | 26 %tmp1 = lshr i32 %X, 8
47 %1 = lshr i64 %0, 16
58 %1 = lshr i64 %0, 32
|
| arm64-vadd.ll | 811 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
822 %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
833 %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>
844 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
[all...] |
| arm64-abi_align.ll | 41 %s1.sroa.1.4.extract.shift = lshr i64 %s1.coerce, 32
43 %s2.sroa.1.4.extract.shift = lshr i64 %s2.coerce, 32
94 %s1.sroa.1.4.extract.shift = lshr i128 %s1.coerce, 32
96 %s2.sroa.1.4.extract.shift = lshr i128 %s2.coerce, 32
151 %s1.sroa.0.4.extract.shift = lshr i64 %s1.coerce.fca.0.extract, 32
155 %s2.sroa.0.4.extract.shift = lshr i64 %s2.coerce.fca.0.extract, 32
204 %s1.sroa.1.4.extract.shift = lshr i128 %s1.coerce, 32
206 %s2.sroa.1.4.extract.shift = lshr i128 %s2.coerce, 32
|
| arm64-shifted-sext.ll | 24 %shr4 = lshr i32 %conv1, 4
49 %shr4 = lshr i32 %conv1, 8
|
| dp-3source.ll | 80 %high = lshr i128 %res, 64
91 %high = lshr i128 %res, 64
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| llvm.AMDGPU.bfe.u32.ll | 201 %shr = lshr i32 %shl, 31
319 ; SI-NOT: lshr
324 %shl = lshr i32 %x, 31
583 %b = lshr i32 %a, 6
593 %c = lshr i32 %a, %b
604 %c = lshr i32 %b, 6
614 %c = lshr i32 %b, 6
624 %c = lshr i32 %b, 11
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| shftopm.ll | 54 %shr = lshr i16 %0, %1
73 %shr = lshr i16 %0, 4
|
| /external/llvm/test/CodeGen/Thumb2/ |
| machine-licm.ll | 110 %5 = lshr i16 %crc_addr.0, 1 ; <i16> [#uses=2]
114 %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1]
|
| 2009-07-30-PEICrash.ll | 139 %52 = lshr i32 %51, 3 ; <i32> [#uses=1]
153 %62 = lshr i32 %61, 3 ; <i32> [#uses=1]
162 %69 = lshr i32 %68, 3 ; <i32> [#uses=1]
171 %76 = lshr i32 %75, 3 ; <i32> [#uses=1]
180 %83 = lshr i32 %82, 3 ; <i32> [#uses=1]
|
| /external/llvm/test/Instrumentation/AddressSanitizer/ |
| basic.ll | 13 ; CHECK: lshr i64 %[[LOAD_ADDR]], 3
46 ; CHECK: lshr i64 %[[STORE_ADDR]], 3
|
| /external/llvm/test/Transforms/InstCombine/ |
| vector-casts.ll | 13 ; The ashr turns into an lshr.
21 ; CHECK: lshr <2 x i64> %b, <i64 1, i64 1>
|
| crash.ll | 8 %tmp8 = lshr i32 %tmp3, 6
9 %tmp9 = lshr i32 %tmp3, 7
265 %3 = lshr i32 %.pre, 19
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| post-inc-icmpzero.ll | 8 ; CHECK: [[r2:%[a-z0-9]+]] = lshr i64 [[r1]], 1
51 %sub.ptr.div39 = lshr exact i64 %sub.ptr.sub, 1
|
| pr2570.ll | 46 lshr i32 2147483647, %13 ; <i32>:19 [#uses=1]
62 lshr i32 2147483647, %p_45 ; <i32>:26 [#uses=1]
145 %.0323 = lshr i32 %73, %75 ; <i32> [#uses=1]
152 %.0320 = lshr i32 %77, %81 ; <i32> [#uses=1]
243 lshr i32 65255, %p_45_addr.0 ; <i32>:128 [#uses=1]
245 %.op = lshr i32 %128, 31 ; <i32> [#uses=1]
|
| /external/llvm/test/Transforms/SCCP/ |
| undef-resolve.ll | 141 ; Make sure lshr produces a possible value
143 %t = lshr i32 undef, 31
|
| /external/llvm/test/Transforms/InstSimplify/ |
| compare.ll | 260 %l = lshr i32 %x, 1
261 %q = lshr i32 %y, 1
320 %l = lshr i32 %x, 1
378 %s = lshr i32 -1, %x
386 %s = lshr i32 %x, 30
394 %s = lshr i32 %x, %x
863 %shr = lshr i32 1, %a
871 %shr = lshr exact i32 30, %a
879 %shr = lshr i32 1, %a
|
| /external/llvm/test/CodeGen/X86/ |
| crash.ll | 17 %shr.i = lshr i64 %add16.i, 8 ; <i64> [#uses=1]
126 %tmp3 = lshr i8 %tmp2, 7
140 %shr8.i = lshr i32 %div.i, 8
459 %1 = lshr i576 %g.0, 64
588 %tmp2 = lshr i64 %tmp, 32
|
| /external/llvm/test/CodeGen/ARM/ |
| vadd.ll | 128 %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
137 %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
146 %shift = lshr <2 x i64> %sum, <i64 32, i64 32>
|
| vsub.ll | 97 %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
106 %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
115 %shift = lshr <2 x i64> %sum, <i64 32, i64 32>
|
| /external/llvm/test/CodeGen/NVPTX/ |
| arithmetic-int.ll | 101 %ret = lshr i64 %a, %b
195 %ret = lshr i32 %a, %b
291 %ret = lshr i16 %a, %b
|
| /external/llvm/test/Transforms/SROA/ |
| big-endian.ll | 50 ; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
214 ; CHECK: %[[LO_SHR:.*]] = lshr i64 34494054408, 32
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 371 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
372 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
397 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
398 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
425 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
426 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2008-07-15-Bswap.ll | 106 lshr i32 0, 30 ; <i32>:10 [#uses=0]
108 lshr i32 0, 28 ; <i32>:12 [#uses=1]
147 lshr i32 %159, 28 ; <i32>:33 [#uses=2]
247 lshr i32 %99, 4 ; <i32>:115 [#uses=1]
249 lshr i32 %102, 5 ; <i32>:117 [#uses=1]
307 lshr i16 %vu16Delta_0.0, 8 ; <i16>:143 [#uses=1]
|
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 203 int LSHR = 123;
367 -1, // lshr, 123
|
