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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
x86-64-simd.d 41 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 12345739 <_start\+0x12345739>
42 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 12345740 <_start\+0x12345740>
160 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 123459ab <_start\+0x123459ab>
161 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 123459b2 <_start\+0x123459b2>
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
x86-64-simd-intel.d 41 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps QWORD PTR \[rip\+0x12345678\],xmm1 # 12345739 <_start\+0x12345739>
42 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps xmm1,QWORD PTR \[rip\+0x12345678\] # 12345740 <_start\+0x12345740>
160 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps QWORD PTR \[rip\+0x12345678\],xmm1 # 123459ab <_start\+0x123459ab>
161 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps xmm1,QWORD PTR \[rip\+0x12345678\] # 123459b2 <_start\+0x123459b2>
x86-64-simd-suffix.d 41 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 12345739 <_start\+0x12345739>
42 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 12345740 <_start\+0x12345740>
160 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 123459ab <_start\+0x123459ab>
161 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 123459b2 <_start\+0x123459b2>
x86-64-simd.d 40 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 12345739 <_start\+0x12345739>
41 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 12345740 <_start\+0x12345740>
159 [ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\) # 123459ab <_start\+0x123459ab>
160 [ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1 # 123459b2 <_start\+0x123459b2>
sse2avx.s 448 movlps %xmm4,(%ecx)
466 movlps (%ecx),%xmm4
1109 movlps QWORD PTR [ecx],xmm4
1127 movlps xmm4,QWORD PTR [ecx]
x86-64-sse2avx.s 448 movlps %xmm4,(%rcx)
490 movlps (%rcx),%xmm4
1152 movlps QWORD PTR [rcx],xmm4
1194 movlps xmm4,QWORD PTR [rcx]
  /external/valgrind/none/tests/amd64/
insn_sse.def 77 movlps m64.ps[12.34,56.78] xmm.ps[11.11,22.22,33.33,44.44] => 1.ps[12.34,56.78,33.33,44.44]
78 movlps xmm.ps[12.34,56.78,43.21,87.65] m64.ps[11.11,22.22] => 1.ps[12.34,56.78]
gen_insn_test.pl 697 print qq| \"movlps %$arg->{argnuml}, %%$arg->{register}\\n\"\n|;
811 print qq| \"movlps %%$result->{register}, %$result->{argnuml}\\n\"\n|;
redundantRexW.stdout.exp 339 after "rex.W movlps (%rdi),%xmm0" (dqws in order [15 .. 0]) {
346 after "rex.W movlps (%rdi),%xmm0" (xmms in order [15..0]) {
365 after "rex.WB movlps %xmm0,(%r10)" (dqws in order [15 .. 0]) {
372 after "rex.WB movlps %xmm0,(%r10)" (xmms in order [15..0]) {
  /external/valgrind/none/tests/x86/
insn_sse.def 77 movlps m64.ps[12.34,56.78] xmm.ps[11.11,22.22,33.33,44.44] => 1.ps[12.34,56.78,33.33,44.44]
78 movlps xmm.ps[12.34,56.78,43.21,87.65] m64.ps[11.11,22.22] => 1.ps[12.34,56.78]
gen_insn_test.pl 666 print qq| \"movlps %$arg->{argnuml}, %%$arg->{register}\\n\"\n|;
775 print qq| \"movlps %%$result->{register}, %$result->{argnuml}\\n\"\n|;
  /external/libyuv/files/source/
row_win.cc 984 movlps qword ptr [edx], xmm0 // U
1054 movlps qword ptr [edx], xmm0 // U
    [all...]
row_posix.cc 793 "movlps %%xmm0,(%1) \n"
    [all...]
  /external/llvm/test/MC/X86/
x86-32-coverage.s     [all...]
  /external/llvm/lib/Target/X86/
README-SSE.txt 109 Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half
716 Consider using movlps instead of movsd to implement (scalar_to_vector (loadf64))
717 when code size is critical. movlps is slower than movsd on core2 but it's one
X86ISelLowering.h 382 MOVLPS,
    [all...]
  /external/elfutils/tests/
testfile44.expect.bz2 
  /external/libvpx/libvpx/third_party/libyuv/source/
row_win.cc     [all...]
row_gcc.cc     [all...]
  /external/elfutils/libcpu/defs/
i386 632 00001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg}
636 00001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m}
    [all...]
  /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/x86/x86asm/testdata/
decode.txt 241 0f1211|223344556677885f5f5f5f5f5f 32 intel movlps xmm2, qword ptr [ecx]
242 0f1211|223344556677885f5f5f5f5f5f 32 plan9 MOVLPS 0(CX), X2
243 0f1211|223344556677885f5f5f5f5f5f 64 gnu movlps (%rcx),%xmm2
244 0f1211|223344556677885f5f5f5f5f5f 64 intel movlps xmm2, qword ptr [rcx]
245 0f1211|223344556677885f5f5f5f5f5f 64 plan9 MOVLPS 0(CX), X2
251 0f1311|223344556677885f5f5f5f5f5f 32 intel movlps qword ptr [ecx], xmm2
252 0f1311|223344556677885f5f5f5f5f5f 32 plan9 MOVLPS X2, 0(CX)
253 0f1311|223344556677885f5f5f5f5f5f 64 gnu movlps %xmm2,(%rcx)
254 0f1311|223344556677885f5f5f5f5f5f 64 intel movlps qword ptr [rcx], xmm2
255 0f1311|223344556677885f5f5f5f5f5f 64 plan9 MOVLPS X2, 0(CX
    [all...]
  /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/x86/x86asm/testdata/
decode.txt 241 0f1211|223344556677885f5f5f5f5f5f 32 intel movlps xmm2, qword ptr [ecx]
242 0f1211|223344556677885f5f5f5f5f5f 32 plan9 MOVLPS 0(CX), X2
243 0f1211|223344556677885f5f5f5f5f5f 64 gnu movlps (%rcx),%xmm2
244 0f1211|223344556677885f5f5f5f5f5f 64 intel movlps xmm2, qword ptr [rcx]
245 0f1211|223344556677885f5f5f5f5f5f 64 plan9 MOVLPS 0(CX), X2
251 0f1311|223344556677885f5f5f5f5f5f 32 intel movlps qword ptr [ecx], xmm2
252 0f1311|223344556677885f5f5f5f5f5f 32 plan9 MOVLPS X2, 0(CX)
253 0f1311|223344556677885f5f5f5f5f5f 64 gnu movlps %xmm2,(%rcx)
254 0f1311|223344556677885f5f5f5f5f5f 64 intel movlps qword ptr [rcx], xmm2
255 0f1311|223344556677885f5f5f5f5f5f 64 plan9 MOVLPS X2, 0(CX
    [all...]
  /art/disassembler/
disassembler_x86.cc 430 opcode1 = "movlps";
    [all...]
  /external/llvm/test/CodeGen/X86/
sse2-intrinsics-x86.ll 585 ; CHECK: movlps
  /external/libchrome/sandbox/win/src/sidestep/
ia32_opcode_map.cpp     [all...]

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