| /external/llvm/test/CodeGen/Mips/ |
| mips64fpldst.ll | 39 ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
42 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
|
| no-odd-spreg.ll | 31 ; ODDSPREG-NOT: swc1
36 ; NOODDSPREG: swc1 $[[T0]],
|
| fp-indexed-ls.ll | 114 ; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]])
121 ; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]])
128 ; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 318 __ swc1(f8, MemOperand(a0, offsetof(T, fc)) ); // fc = fa + fb.
322 __ swc1(f10, MemOperand(a0, offsetof(T, fd)) ); // fd = fc - (-fb).
324 __ swc1(f4, MemOperand(a0, offsetof(T, fb)) ); // fb = fa.
330 __ swc1(f10, MemOperand(a0, offsetof(T, fe)) ); // fe = fd * 120
333 __ swc1(f12, MemOperand(a0, offsetof(T, ff)) ); // ff = fe / fa
336 __ swc1(f14, MemOperand(a0, offsetof(T, fg)) );
[all...] |
| test-assembler-mips64.cc | 327 __ swc1(f8, MemOperand(a0, offsetof(T, fc)) ); // fc = fa + fb.
331 __ swc1(f10, MemOperand(a0, offsetof(T, fd)) ); // fd = fc - (-fb).
333 __ swc1(f4, MemOperand(a0, offsetof(T, fb)) ); // fb = fa.
339 __ swc1(f10, MemOperand(a0, offsetof(T, fe)) ); // fe = fd * 120
342 __ swc1(f12, MemOperand(a0, offsetof(T, ff)) ); // ff = fe / fa
345 __ swc1(f14, MemOperand(a0, offsetof(T, fg)) );
[all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2.S | [all...] |
| /external/llvm/test/MC/Mips/ |
| mips-memory-instructions.s | 12 # CHECK: swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4]
19 swc1 $f2, 16($5)
|
| nacl-mask.s | 117 swc1 $f0, 0($4)
144 # CHECK-NEXT: swc1 $f0, 0($4)
|
| micromips-fpu-instructions.s | 22 # CHECK-EL: swc1 $f2, 4($6) # encoding: [0x46,0x98,0x04,0x00]
87 # CHECK-EB: swc1 $f2, 4($6) # encoding: [0x98,0x46,0x00,0x04]
150 swc1 $f2, 4($6)
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| loadstore2.ll | 65 ; CHECK: swc1 $f[[REGf]], 0(${{[0-9]+}})
|
| simplestorefp1.ll | 23 ; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
|
| /art/compiler/optimizing/ |
| optimizing_cfi_test_expected.inc | 164 // 0x00000010: swc1 f22, +8(r29)
165 // 0x00000014: swc1 f23, +12(r29)
166 // 0x00000018: swc1 f20, +0(r29)
167 // 0x0000001c: swc1 f21, +4(r29)
380 // 0x00000010: swc1 f22, +8(r29)
381 // 0x00000014: swc1 f23, +12(r29)
382 // 0x00000018: swc1 f20, +0(r29)
383 // 0x0000001c: swc1 f21, +4(r29)
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 207 swc1 \reg, 0(AT)
252 swc1 \reg, 0(AT)
|
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 706 TEST_F(AssemblerMIPSTest, Swc1) {
707 DriverStr(RepeatFRIb(&mips::MipsAssembler::Swc1, -16, "swc1 ${reg1}, {imm}(${reg2})"), "Swc1");
[all...] |
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float-varargs.ll | 115 ; NEW-DAG: swc1 $f12, 4([[R2]])
157 ; ALL-DAG: swc1 [[FTMP1]], 8([[R2]])
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrFPU.td | 21 def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>,
|
| MipsScheduleP5600.td | 255 // sdxc1, sdc1, st.[bhwd], swc1, swxc1
355 // swc1, swxc1, st.[bhwd]
|
| MipsInstrFPU.td | 398 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
611 def : StoreRegImmPat<SWC1, f32>;
|
| /external/valgrind/none/tests/mips32/ |
| vfp.c | 205 // swc1 $f0, 0($t0)
213 "swc1 $f0, "#offset"($t0) \n\t" \
219 printf("swc1 $f0, 0($t0) :: out: 0x%x\n", \
425 printf("SWC1\n");
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| sb.s | 115 swc1 $4,0
|
| micromips.s | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 230 case Mips::SWC1:
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 114 swc1 $f6,-8465($24)
|
| /external/v8/src/crankshaft/mips/ |
| lithium-gap-resolver-mips.cc | 215 __ swc1(kLithiumScratchDouble, destination_operand);
|
